High Input/Output, Low Profile Package-On-Package Semiconductor System

A method for fabricating a semiconductor package-on-package system, comprising the steps of:

• fabricating a first subsystem comprising the steps of:
• providing a strip of an insulating sheet-like carrier having a first and a second surface, and including conductive vertical vias and conductive horizontal traces;
• the carrier further having solderable terminals on the second surface;
• the first surface having sites for assembling semiconductor subsystems, each site including a central portion having an area and a peripheral portion, with bondable contact pads on the central surface portions;
• providing a plurality of insulating frames having conductive vertical vias and conductive horizontal lines, each frame further having a height and a third surface with solderable terminals having a pitch center-to-center;
• laminating a frame to each peripheral portion of the assembly sites, exposing the respective central portion;
• providing a plurality of first chips having a first height;
• assembling a first chip to the central portion of each site, while electrically connecting the first chip to contact pads in the central portion;
• providing a plurality of second chips having a second height;
• assembling a second chip on top of each first chip and electrically bonding selected connections to contact pads in the central portion so that the sum of the first and the second chip height approximates the frame height;
• encapsulating each site by filling the volume determined by the area of the central surface portion and the height of the frame with encapsulation compound;
• and
• singulating each individual site from the strip, thus creating a plurality of first subsystems, each including a strip portion as first substrate;
• providing a second subsystem comprising a packaged semiconductor device including:
• a second insulating substrate having a fourth surface with solderable terminals in locations matching the terminals on the third surface of the first subsystems;
• at least one semiconductor chip disposed on the second substrate;
• and
• solder connectors of a first reflow temperature attached to the terminals on the fourth surface;
• fabricating a package-on-package system comprising the steps of:
• aligning the solder connectors on the terminals on the fourth surface of a second subsystem with the terminals on the third surface of a first subsystem;
• increasing the temperature to reflow the solder connectors and interconnect the third and fourth surfaces;
• and
• cooling the temperature to ambient temperature so that the solder connectors have a height less than the pitch of the terminals.