Method of manufacturing a semiconductor device
AssigneeRenesas Technology Corp.
InventorsHideki Yasuoka, Keiichi Yoshizumi, Masami Koketsu
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AssigneeRenesas Technology Corp.
InventorsHideki Yasuoka, Keiichi Yoshizumi, Masami Koketsu
Estimating the term…
With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, n+ type semiconductor regions, each having a conduction type opposite to p+ type semiconductor regions for a source and drain of a high breakdown voltage pMIS, are disposed in a boundary region between each of trench type isolation portions at both ends, in a gate width direction, of a channel region of the high breakdown voltage pMIS and a semiconductor substrate at positions spaced away from p− type semiconductor regions, each having a field relaxing function, of the high breakdown voltage pMIS, so as not to contact the p− type semiconductor regions (on the drain side, in particular). The n+ type semiconductor regions extend to positions deeper than the trench type isolation portions.
A semiconductor device having a first MISFET comprising:
Dependencies are inferred from the claim text.