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US 2008/0258207 A1Published application
Block Contact Architectures for Nanoscale Channel Transistors
AssigneeIntel Corporation
InventorsMarko Radosavljevic, Amlan Majumdar, Brian S. Doyle, Jack Kavalieros, Mark L. Doczy, Justin K. Brask, Uday Shah, Suman Datta, Robert S. Chau
Life of this patent
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Abstract
A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.
Claims20
An apparatus comprising:
- a plurality of parallel semiconductor bodies, each of said plurality of parallel bodies having a top surface and a pair of laterally opposite sidewalls, each of said parallel bodies having a channel portion between a source region and a drain region;
- a single gate electrode formed adjacent to and over said channel region of each of said plurality of bodies;
- a metal source contact coupled to and extending between said source regions of each of said plurality of parallel bodies;
- and
- a metal drain contact coupled to and extending between said drain regions of each of said plurality of parallel bodies, wherein at least one of the metal source contact or metal drain contact has a length that is substantially smaller than a width.
2 more elements
An apparatus comprising:
- a plurality of parallel semiconductor bodies, each of the plurality having a top surface and a pair of laterally opposite sidewalls, each of said plurality having a channel portion between a source region and a drain region;
- a single gate electrode formed adjacent to and over said channel region of each of said plurality of bodies;
- a first source contact to a source region of at least a first of the plurality of parallel semiconductor bodies;
- a second source contact to a source region of at least a second, different than the first, of the plurality of parallel semiconductor bodies;
- a drain contact to a drain region of at least the first and second of the plurality of parallel semiconductor bodies.
2 more elements
An apparatus comprising:
- a plurality of parallel semiconductor bodies, each of the plurality having a top surface and a pair of laterally opposite sidewalls, each of said plurality having a channel portion between a source region and a drain region;
- a single gate electrode formed adjacent to and over said channel region of each of said plurality of bodies;
- a first drain contact to a drain region of at least a first of the plurality of parallel semiconductor bodies;
- a second drain contact to a drain region of at least a second, different than the first, of the plurality of parallel semiconductor bodies;
- a source contact to a source region of at least the first and second of the plurality of parallel semiconductor bodies.
2 more elements
Dependencies are inferred from the claim text.