US 2008/0258205 A1Published application

Non-volatile semiconductor memory device

AssigneeRenesas Technology Corp.

InventorsTetsuya ISHIMARU, Yasuhiro SHIMAMOTO, Kan YASUI

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Abstract

An erase current of a non-volatile semiconductor memory device is decreased. A memory cell of the non-volatile semiconductor memory device comprises a source region and a drain region formed in a semiconductor substrate. Over a portion of the semiconductor substrate between the source region and the drain region, a select gate electrode is formed via a gate dielectric film. On a side wall of the select gate electrode, a memory gate electrode is formed via a bottom silicon oxide film and a charge-trapping silicon oxynitride film. In the memory cell configured as above, erase operation is performed as follows. By applying a positive voltage to the memory gate electrode, holes are injected from the memory gate electrode into the silicon oxynitride film to decrease a threshold voltage in a program state to a certain level. Thereafter, hot holes generated by a band-to-band tunneling phenomenon are injected into the silicon oxynitride film and the erase operation is completed.

Claims20

Dependent claims

A non-volatile semiconductor memory device comprising:

a memory cell, comprising:
(a) a first semiconductor region and a second semiconductor region formed in a semiconductor substrate so as to be separated from each other;
(b) a first dielectric film formed over an upper portion of the semiconductor substrate over a portion between the first semiconductor region and the second semiconductor region;
and
(c) the first gate electrode formed over the first dielectric film,
wherein the first dielectric film comprises:
(b1) a silicon oxide film;
and
(b2) the charge accumulation film with a function of accumulating a charge formed over the silicon oxide film and directly contacting with a first gate electrode,
wherein first operation of making a threshold voltage of the memory cell lower than a threshold voltage of the memory cell in a program state is performed by applying a positive voltage larger than a voltage applied to the semiconductor substrate to the first gate electrode, and then second operation of making the threshold voltage of the memory cell still lower is performed by injecting holes generated using a band-to-band tunneling phenomenon in the semiconductor substrate into the charge accumulation film so as to complete erase operation.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/103,697Filed 15 Apr 2008
Priority: JP JP2007-10814517 Apr 2007
Published: 23 Oct 2008
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10D 30/69
Insulated-gate field-effect transistors [IGFET]: iGFETs having charge trapping gate insulators, e.g. MNOS transistors
G11C 16/14
Programming or data input circuits: circuits for erasing electrically, e.g. erase voltage switching circuits
H10D 30/0413
Of FETs having insulated gates [IGFET]: of FETs having charge-trapping gate insulators, e.g. MNOS transistors
H10D 30/696
Characterised by the shapes, relative sizes or dispositions of the gate electrodes: having at least one additional gate, e.g. program gate, erase…