Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device comprising:

• a semiconductor substrate having an upper surface in which a plurality of first trenches are formed such that an element forming region is defined, the first trenches having respective sidewalls;
• an element isolation insulating film buried in the first trenches;
• a floating gate electrode formed on the element forming region with a first gate insulating film being interposed therebetween, so as to extend along the sidewalls of the first trenches;
• a second gate insulating film formed on upper portions of the floating gate electrode and the element isolation insulating film;
• and
• a control gate electrode formed on the second gate insulating film,
• wherein the element isolation insulating film has an upper end located lower than an upper surface of the floating gate electrode and the upper end of the element isolation insulating film includes a sidewall having such a height as to be in contact with the floating gate electrode;
• the element isolation insulating film includes a central portion in which a second trench is formed, the second trench having a bottom located lower than the upper surface of the semiconductor substrate;
• the floating gate electrode includes a sidewall further including an upper portion opposed to the control gate electrode with the second gate insulating film being interposed therebetween, the sidewall of the floating gate electrode including a lower portion opposed to the control gate electrode with the element isolation insulating film and the second gate insulating film being interposed therebetween in turn;
• the control gate electrode is buried in the second trench with the second gate insulating film being interposed therebetween, the control gate electrode having a lower end including a sidewall opposed to a sidewall of the trench of the semiconductor substrate with the second gate insulating film and the element isolation insulating film being interposed therebetween;
• the element isolation insulating film includes a portion located higher than an upper surface of the first gate insulating film, said portion of the element isolation insulating film having a film thickness in a direction along the upper surface of the semiconductor substrate, said film thickness being smaller than a film thickness of the second gate insulating film;
• and
• the semiconductor substrate includes a portion located between the sidewall of the trench and a side of the second trench, said portion of the semiconductor substrate having a film thickness in a direction along the upper surface of the semiconductor substrate, said film thickness being larger than a film thickness of the second gate insulating film.

A nonvolatile semiconductor memory device comprising:

• a semiconductor substrate having an upper surface in which a plurality of first trenches are formed such that an element forming region is defined, the first trenches having respective sidewalls;
• an element isolation insulating film buried in the first trenches;
• a floating gate electrode formed on the element forming region with a first gate insulating film being interposed therebetween, so as to extend along the sidewalls of the first trenches;
• a second gate insulating film formed on upper portions of the floating gate electrode and the element isolation insulating film;
• and
• a control gate electrode formed on the second gate insulating film,
• wherein the element isolation insulating film has an upper end located lower than an upper surface of the floating gate electrode and the upper end of the element isolation insulating film includes a sidewall having such a height as to be in contact with the floating gate electrode;
• the element isolation insulating film includes a central portion in which a second trench is formed, the second trench having a bottom located lower than the upper surface of the semiconductor substrate;
• the second trench includes a pair of sidewalls and a distance between the sidewalls is gradually reduced from the upper end toward the bottom of the second trench;
• the floating gate electrode includes a sidewall further including an upper portion opposed to the control gate electrode with the second gate insulating film being interposed therebetween, the sidewall of the floating gate electrode including a lower portion opposed to the control gate electrode with the element isolation insulating film and the second gate insulating film being interposed therebetween in turn;
• the control gate electrode is buried in the second trench with the second gate insulating film being interposed therebetween, the control gate electrode having a lower end including a sidewall opposed to a sidewall of the trench of the semiconductor substrate with the second gate insulating film and the element isolation insulating film being interposed therebetween;
• the element isolation insulating film includes a portion located higher than an upper surface of the first gate insulating film, said portion of the element isolation insulating film having a film thickness in a direction along the upper surface of the semiconductor substrate, said film thickness being smaller than a film thickness of the second gate insulating film;
• and
• the semiconductor substrate includes a portion located between the sidewall of the trench and a side of the second trench, said portion of the semiconductor substrate having a film thickness in a direction along the upper surface of the semiconductor substrate, said film thickness being larger than a film thickness of the second gate insulating film.