Semiconductor memory device and method of manufacturing the same

A semiconductor memory device comprising:

• a semiconductor substrate having a memory cell region and a peripheral circuit region;
• a plurality of first trenches formed in said memory cell region on the surface of said semiconductor substrate at predetermined intervals in a strip-shaped manner along a first direction;
• first element-isolating insulating films respectively buried in said first trenches so that the top surface thereof is formed so as to be higher than the top surface of said semiconductor substrate;
• a plurality of floating gate electrodes formed on the surface of said semiconductor substrate between said first trenches through a gate-insulating film at predetermined intervals along said first direction, so that the top surface thereof is higher than said first element-isolating insulating films;
• a plurality of control gate electrodes formed above said floating gate electrodes through an inter-electrode insulating film at predetermined intervals in a strip-shaped manner along a second direction orthogonal to said first direction;
• second trenches formed in said peripheral circuit region on the surface of said semiconductor substrate;
• second element-isolating insulating films buried in said second trenches so that the top surface thereof is formed to be level with the height of said first element-isolating insulating films;
• first lower conducting layers formed on the surface of said semiconductor substrate in areas partitioned by said second trenches through a gate-insulating film, so that the top surface height thereof is the same as the height of said floating gate electrodes;
• first upper conducting layers formed above said first lower conducting layers;
• third trenches formed in said peripheral circuit region on the surface of said semiconductor substrate;
• second lower conducting layers formed on the surface of said semiconductor substrate in areas partitioned by said third trenches through a gate-insulating film, so that the top surface height thereof is the same as the height of said floating gate electrodes;
• third element-isolating insulating films buried in said third trenches and formed so that the top surface height thereof is the same as the height of said second lower conducting layers;
• and
• second upper conducting layers formed above said second lower conducting layers so as to be electrically connected with said first lower conducting layers.