Method of manufacturing a device by locally heating one or more metallization layers and by means of selective etching

A method of manufacturing an SiC diode, comprising:

• generating p-doped regions in an n-doped SiC semiconductor substrate;
• thermally annealing the semiconductor substrate;
• vapor-depositing or sputtering one or more metallization layers, which are suited to form an ohmic contact with the p-doped regions, onto a first area;
• locally heating the one or more metallization layers in a local area bordering on the p-doped regions to form a substrate/metallization-layer compound or a metallization-layer compound, the compound comprising an etch-selectivity toward an etching medium which is different to that of the one or more metallization layers outside the local area;
• removing the one or more metallization layers outside the p-doped regions by etching with the etching medium;
• depositing a further metal, which is suited to form a blocking Schottky contact with an n-doped region of the SiC semiconductor substrate, onto the n-doped region and onto the one or more metallization layers on the p-doped regions;
• reinforcing the further metal by applying a metal at a thickness larger than a thickness of the further metal.

A method of manufacturing an SIC-JFET, comprising:

• creating a trough within an SiC semiconductor substrate having a first doping characteristic which differs from a second doping characteristic with which a semiconductor region surrounding the trough is doped;
• creating, within the trough, a gate area which is doped with the second doping characteristic;
• depositing one or more metallization layers both to the trough and to the gate area;
• locally heating one source contact area and a separate drain contact area within the trough, and a separate gate contact area within the gate region so as to obtain a semiconductor-substrate/metallization-layer compound, the compound comprising an etch-selectivity toward an etching medium which is different to that of the one or more metallization layers outside the contact areas;
• and
• removing the one or more metallization layers outside the contact areas by etching with the etching medium to form a source contact, a drain contact and a gate contact.

A method of manufacturing a vertical SiC-JFET, comprising:

• creating a well having a first doping characteristic which differs from a second doping characteristic with which a semiconductor region surrounding the well is doped;
• creating, above the well and separated from the well by a semiconductor region, a gate area which is doped with the first doping characteristic;
• depositing one or more metallization layers at least on the gate area;
• locally heating a defined gate contact region in the gate area so as to obtain a semiconductor-substrate/metallization-layer compound, the compound comprising an etch-selectivity toward an etching medium which is different to that of the one or more metallization layers outside the contact areas;
• and
• removing the one or more metallization layers outside the gate contact region by etching with the etching medium to form a gate contact.