Stressed mos device
AssigneeAdvanced Micro Devices, Inc.
InventorsIgor PEIDOUS, Linda R. BLACK, Frank WIRBELEIT
Life of this patent
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Abstract
A stressed MOS device is provided that includes a silicon substrate, a gate electrode and an epitaxial layer of stress inducing monocrystalline semiconductor material. The silicon substrate is characterized by a monocrystalline silicon lattice constant. The gate electrode overlies a silicon channel region at the surface of the silicon substrate. The epitaxial layer of stress inducing monocrystalline semiconductor material is grown in the silicon substrate. The epitaxial layer of stress inducing monocrystalline semiconductor material has a lattice constant greater than the monocrystalline silicon lattice constant, and extends under the silicon channel region.
Claims14
A stressed MOS transistor comprising:
- a substrate having a surface, the substrate comprising a monocrystalline semiconductor material having a first lattice constant;
- a channel region formed of the monocrystalline silicon material adjacent the surface;
- and
- a stress inducing monocrystalline semiconductor material having a second lattice constant greater than the first lattice constant grown under the channel region and exerting a horizontal tensile stress on the channel region.
A stressed MOS device, comprising:
- a silicon substrate characterized by a monocrystalline silicon lattice constant;
- a gate electrode overlying a silicon channel region at the surface of the silicon substrate;
- and
- an epitaxial layer of stress inducing monocrystalline semiconductor material in the silicon substrate extending under the silicon channel region, the stress inducing monocrystalline semiconductor material having a lattice constant greater than the monocrystalline silicon lattice constant.
A stressed MOS device, comprising:
- a silicon substrate comprising an N-type region and a P-type region, the P-type region including a channel region;
- a first gate electrode overlying the N-type region;
- first recesses in the silicon substrate in alignment with the first gate electrode;
- a second gate electrode overlying the P-type region, the second gate electrode overlying the channel region;
- and
- second recesses in the silicon substrate in alignment with the second gate electrode, wherein the second recesses extend under the channel region;
- and
- a layer of a monocrystalline stress inducing semiconductor material that fills the first recesses and the second recesses.
Dependencies are inferred from the claim text.