Thin film transistor array panel and fabricating method thereof, and flat panel display with the same

A flat panel display, comprising:

• an organic thin film transistor array panel;
• a common electrode panel facing the organic thin film transistor array panel;
• and
• electrophoretic particles disposed between the organic thin film transistor array panel and the common electrode panel,
• wherein the organic thin film transistor array panel comprises
• a substrate,
• a gate line formed on the substrate, extending in a first direction, and including a gate electrode,
• a storage electrode line formed on the substrate,
• a gate insulation layer covering the gate line and the storage electrode line,
• a data line formed on the gate insulation layer, extending in a second direction to cross the gate line, and including a source electrode,
• a drain electrode facing the source electrode,
• a bank including a first hole exposing the source electrode and the drain electrode,
• an organic semiconductor formed in the first hole and connected to the source electrode and the drain electrode,
• a passivation layer covering the bank and the organic semiconductor, and
• a pixel electrode formed on the protective layer and connected to the drain electrode.

A manufacturing method for a thin film transistor array panel, comprising:

• forming a gate line and a storage electrode line parallel to the gate line on a substrate;
• forming a gate insulation layer on the gate line, the storage electrode line, and the substrate;
• forming a data line, a source electrode, and a drain electrode on the gate insulation layer;
• forming a bank having a first hole and a second hole on the gate insulation layer, the data line, the source electrode, and the drain electrode;
• forming an organic semiconductor in the first hole of the bank;
• forming a passivation layer having a hole aligned with the second hole of the bank on the bank and the organic semiconductor;
• and
• forming a pixel electrode on the passivation layer.

A thin film transistor array panel, comprising:

• a substrate;
• a gate line formed on the substrate, extending in a first direction, and including a gate electrode;
• a gate insulation layer formed on the gate line and containing fluorine in a portion thereof;
• a data line formed on the gate insulation layer, extending in a second direction to cross the gate line, and including a source electrode;
• a drain electrode separated from the data line and facing the source electrode;
• a bank including a first hole exposing the source electrode and the drain electrode and disposed on the source electrode and the drain electrode;
• a semiconductor formed in the first hole and connected to the source electrode and the drain electrode to form a channel of a thin film transistor;
• a passivation layer covering the bank and the semiconductor;
• and
• a pixel electrode formed on the passivation layer and connected to the drain electrode.

A manufacturing method for a thin film transistor array panel, comprising:

• A) forming a gate line including a gate electrode on a substrate;
• B) forming a gate insulation layer on the gate line and the substrate;
• C) sequentially depositing a first conductive layer and a second conductive layer on the gate insulation layer;
• D) patterning the first conductive layer and the second conductive layer to form a data line, a source electrode, and a drain electrode composed of the first conductive layer and the second conductive layer, and a block portion disposed over the gate electrode, connected to the source electrode and the drain electrode, and composed of the first conductive layer;
• E) forming a bank having a first hole exposing the source electrode, the drain electrode, and the block portion;
• F) performing fluorine plasma treatment on the bank;
• G) etching the first conductive layer by using the second conductive layer exposed through the first hole as an etching mask to remove the block portion;
• H) forming a semiconductor in the first hole;
• I) forming a passivation layer on the bank and the semiconductor;
• and
• I) forming a pixel electrode on the passivation layer.

A flat panel display, comprising:

• a thin film transistor array panel;
• a common electrode panel facing the thin film transistor array panel;
• and
• electrophoretic particles disposed between the organic thin film transistor array panel and the common electrode panel,
• wherein the thin film transistor array panel comprises
• a substrate,
• a gate line formed on the substrate, extending in a first direction, and including a gate electrode,
• a gate insulation layer formed on the gate line and containing fluorine in a portion thereof,
• a data line formed on the gate insulation layer, extending in a second direction to cross the gate line, and including a source electrode,
• a drain electrode separated from the data line and facing the source electrode,
• a bank including a first hole exposing the source electrode and the drain electrode and disposed on the source electrode and the drain electrode,
• a semiconductor formed in the first hole and connected to the source electrode and the drain electrode to form a channel of a thin film transistor,
• a passivation layer covering the bank and the semiconductor, and
• a pixel electrode formed on the passivation layer and connected to the drain electrode.