Phase-Change Memory Device

A phase-change memory device comprising:

• a semiconductor substrate;
• a plurality of semiconductor layers formed in said semiconductor substrate so that these are arrayed in a matrix form while being partitioned by an element isolation dielectric film;
• diodes each formed at its corresponding semiconductor layer with a metal electrode as a terminal electrode, the metal electrode being formed at part of a surface of each said semiconductor layer;
• a plurality of first wiring lines provided to commonly connect said diodes as arrayed in one direction of the matrix;
• an interlayer dielectric film covering said first wiring lines;
• metal plugs buried in space portions of said first wiring lines of said interlayer dielectric film and being in ohmic contact with each said semiconductor layer;
• a chalcogenide layer being formed above said interlayer dielectric film and having its bottom surface in contact with said metal plugs;
• and
• a plurality of second wiring lines provided to cross said first wiring lines while being in contact with an upper surface of said chalcogenide layer.

A phase-change memory device comprising:

• an insulative substrate;
• a plurality of first wiring lines formed in parallel with each other above said insulative substrate;
• memory cells being formed over each said first wiring line so that one end is connected to each said first wiring line, each said memory cell having a stacked structure of a variable resistive element and a diode, said variable resistive element storing as information a resistance value determined due to phase change between crystalline and amorphous states thereof;
• and
• a plurality of second wiring lines formed over said memory cells to commonly connect together the other end portions of said memory cells arrayed in a direction crossing said first wiring lines.

A phase-change memory device comprising:

• an insulative substrate;
• and
• a plurality of memory cell arrays stacked over said insulative substrate, wherein
• each said memory cell array comprises:
• a plurality of first wiring lines extending in parallel with each other;
• a plurality of memory cells being formed above each said first wiring line in such a manner that one end is connected to each said first wiring line and each comprising a stacked structure of a variable resistive element and a diode, said variable resistive element storing as information a resistance value determined due to phase change between crystalline! and amorphous states thereof;
• and
• a plurality of second wiring lines formed above said memory cells to commonly connect the other ends of said memory cells arrayed in a direction crossing said first wiring lines.

A phase-change memory comprising:

• a substrate;
• a plurality of first parallel wiring lines formed above said substrate;
• a plurality of second parallel wiring lines formed above said substrate to cross the first wiring lines while being electrically insulated therefrom;
• a plurality of memory cells disposed at respective crossing points of said first wiring lines and said second wiring lines in such a manner that one ends thereof are connected to said first wiring lines and the other ends to said second wiring lines, said memory cell comprising a variable resistive element for storing a resistance value determined due to phase change between crystalline and amorphous states thereof, and a diode connected in series to said variable resistive element;
• and
• selector circuits for fixing said first wiring lines to a state lower in potential than said second wiring lines when nonselected and for selectively supplying positive and negative logic pulses to said first and second wiring lines respectively during data reading or writing.

A phase-change memory device comprising an insulative substrate and a plurality of memory cell arrays stacked over said insulative substrate, wherein

• each said memory cell array comprises:
• a plurality of first wiring lines extending in parallel with each other;
• a plurality of memory cells formed above said first wiring line in such a manner that one ends are connected to said first wiring lines, each said memory cell comprising a stacked structure of a variable resistive element and a diode, said variable resistive element storing as information a resistance value determined due to phase change between crystalline and amorphous states thereof;
• and
• a plurality of second wiring lines formed above said memory cells to commonly connect the other ends of said memory cells arrayed in a direction crossing said first wiring lines, and wherein
• write and read of multiple-value information are performed by combination of a high resistance state and a low resistance state of the respective memory cells accessed simultaneously in said plurality of memory cell arrays.

A memory device comprising:

• a semiconductor substrate;
• a plurality of semiconductor regions formed on the semiconductor substrate to be separated from each other by an insulating film buried in the semiconductor substrate;
• diodes formed on the semiconductor regions;
• a plurality of first wiring lines formed on the substrate to couple the diodes arranged in one direction;
• an interlayer dielectric film formed to cover the first wiring lines;
• metal plugs buried in the interlayer dielectric film to be in contact with the semiconductor layers;
• variable resistance elements formed on the metal plugs;
• and
• a plurality of second wiring lines formed on the variable resistance elements to couple them arranged in the direction crossing the first wiring lines.

A method for fabricating a memory device comprising:

• burying an insulating film in a semiconductor substrate to partition it into a plurality of semiconductor regions;
• forming diodes on the semiconductor regions;
• forming a plurality of first wiring lines on the substrate to couple the diodes arranged in one direction;
• forming an interlayer dielectric film to cover the first wiring lines;
• burying metal plugs in the interlayer dielectric film to be in contact with the semiconductor regions;
• forming variable resistance elements on the metal plugs to constitute memory cells together with the diodes;
• and
• forming a plurality of second wiring lines on the variable resistance elements to couple them arranged in the direction crossing the first wiring lines.

A memory device comprising;

• a substrate;
• a plurality of first wiring lines formed above the substrate;
• a first interlayer dielectric film formed between the first wiring lines;
• memory cells formed on the first wiring lines, each said memory cell having a stacked structure of a variable resistance element and a diode;
• a second interlayer dielectric film formed around the memory cells;
• and
• a plurality of second wiring lines formed over the memory cells and the second interlayer dielectric film to cross the first wiring lines and couple the memory cells arranged in the direction the second wiring lines.

A method for fabricating a memory device comprising:

• forming a plurality of first wiring lines above a substrate;
• forming a first interlayer dielectric film between the first wiring lines;
• forming memory cells on the first wiring lines, the memory cell having a stacked structure of a variable resistance element and a diode;
• forming a second interlayer dielectric film around the memory cells;
• and
• forming a plurality of second wiring lines over the memory cells and the second interlayer dielectric film to cross the first wiring lines and couple the memory cells arranged in the direction the second wiring lines.

A memory device comprising a substrate and a plurality of memory cell arrays stacked above the substrate, wherein

• each said memory cell array comprises:
• a plurality of first wiring lines formed on an insulative surface of an underlying substrate;
• a first interlayer dielectric film buried between the first wiring lines;
• memory cells formed on the first wiring lines, each said memory cell having a variable resistance element to be set at a resistance value;
• a second interlayer dielectric film formed around the memory cells;
• and
• a plurality of second wiring lines formed over the memory cells and the second interlayer dielectric film to couple the memory cells arranged in the direction of the second wiring lines.

A memory device comprising:

• a substrate;
• a plurality of memory cell arrays stacked above the substrate, each said memory cell array including first wiring lines and second wiring lines crossing each other, and memory cells disposed between the first wiring lines and the second wiring lines at crossing points thereof, each said memory cell having a stacked structure of a variable resistance element and a diode;
• and
• selector circuits formed on the substrate for fixing the first and second wiring lines in potential in such a manner as to reverse-bias the diodes in non-selected memory cells, and for driving a first wiring line and a second wiring line in a memory cell array in such a manner as to forward-bias the diode in a selected memory cell during data reading or writing.

A memory device comprising:

• a substrate;
• a memory cell array formed above the substrate to have first wiring lines and second wiring lines crossing each other, and memory cells disposed between the first wiring lines and the second wiring lines at crossing points thereof, each said memory cell having a stacked structure of a variable resistance element and a diode;
• and
• a sense amplifier formed on the substrate, wherein
• the sense amplifier comprises at least one of:
• a first current detecting circuit for comparing a current flowing in a selected first wiring line with a reference current when a positive logic pulse and a negative logic pulse are applied to the selected first wiring line and a selected second wiring line, respectively, to forward-bias the diode in a selected memory cell;
• and
• a second current detecting circuit for comparing a current flowing in a selected second wiring line with a reference current when a positive logic pulse and a negative logic pulse are applied to a selected first wiring line and the selected second wiring line, respectively, to forward-bias the diode in a selected memory cell.

A memory device comprising:

• a substrate;
• a plurality of memory cell arrays stacked above the substrate, each said memory cell array including memory cells arranged therein, the memory cell having a stacked structure of a variable resistance element and a diode;
• and
• a sense amplifier configured to sense memory cell data, wherein
• multi-value data is storable in the memory cells selected one by one from the respective memory cell arrays, the multi-value data being defined by a combination of resistance states in the respective memory cells.

A memory device comprising:

• a substrate;
• a plurality of memory cell arrays stacked above the substrate, each said memory cell array including memory cells arranged therein, each said memory cell having a stacked structure of a variable resistance element and a diode;
• and
• a write circuit configured to write a multi-value data defined by multiple bits storable one by one in the memory cells selected from the respective memory cell arrays.

A memory device comprising:

• a substrate;
• a plurality of memory cell arrays stacked above the substrate, each said memory cell array having bit lines coupled to one ends of memory cells and word lines coupled to the other ends, each said memory cell having a stacked structure of a variable resistance element and a diode, the memory cell arrays being partitioned in the bit line direction and in the word line direction into a plurality of cell blocks each serving as an access unit;
• a bit line select circuit formed on the substrate to select one of the bit lines in one of the cell blocks;
• and
• a word line select circuit formed on the substrate to select one of the word lines contained in of the cell blocks.

A memory device comprising:

• a substrate;
• and
• a plurality of memory cell arrays stacked above the substrate, each said memory cell array having bit lines coupled to one ends of memory cells and word lines coupled to the other ends, each said memory cell having a stacked structure of a variable resistance element and a diode, wherein
• the memory cell arrays are partitioned in the bit line direction and in the word line direction into a plurality of cell blocks each with a three dimensional address space, and wherein
• one of one-dimensional addresses defined in a two-dimensional address space of each said cell block with a three-dimensional address space is defined as a key address, in which a key string data is stored, and such a data search mode is adapted as to scan the one-dimensional addresses in the two-dimensional address space to detect the key string data, and then scan the remaining one-dimensional addresses to detect data belonging to the key string data.

A memory device comprising:

• a substrate;
• and
• at least one memory cell array formed above the substrate to have bit lines coupled to one ends of memory cells and word lines coupled to the other ends, each said memory cell including a variable resistance element, wherein
• one ends of a group of the memory cells are coupled in common to a word line via a selecting device while the other ends are coupled to different bit lines, respectively, in each said memory cell array.