Interrupt Control

Abstract

An interrupt controller (1) is adapted to control the execution of interrupt requests (11, 12) of differing criticality by a processor (7) which is required to execute tasks (3, 17) of differing criticality under the control of a computer operating system (5); the interrupt controller being adapted to recognize critical (11) and non-critical (12) interrupt requests originating from different interrupt sources, and to recognize when the processor (7) is required to execute each of critical (3) and non-critical tasks (17); the interrupt controller being further adapted to pass critical interrupt requests (11) to the processor (7) for execution in preference to non-critical interrupt requests (12), to block non-critical interrupt requests (12) to the processor when they coexist with critical interrupt requests (11) or the processor (7) is required to execute critical tasks (3), and to pass non-critical interrupt requests (12) to the processor (7) when they do not coexist with any critical interrupt requests (11) and the processor (7) has no critical tasks (3) to be executed. The interrupt controller (1) is preferably implemented in hardware and its operation is transparent to the processor (7).

Dependencies are inferred from the claim text.