# US 2008/0189588 A1 · Bit error prevention method and information processing apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2008/0189588 A1 - Document ID: US20080189588A1 - Status: Published application - Kind: A1 - Application number: 11/968,964 - Filed: 2008-01-03 - Published: 2008-08-07 - Earliest claimed: 2007-02-07 - Assignees: MegaChips Corporation - Inventors: Shinji TANAKA; Tetsuo Furuichi - Web page: https://patentgrep.com/patent/US20080189588A1 ## CPC - G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)} - G11C 2029/0411: {Online error correction} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Whether the comparison value of temporarily stored data which is read out from a flash memory by a host system exceeds a threshold value related to a bit error or not is checked, and if the comparison value exceeds the threshold value, the temporarily stored data which is read out is rewritten into the flash memory. If the temporarily stored data has an error, the error is corrected by an error correction part and then the data is rewritten. The threshold value includes, e.g., the number of readouts, the number of bit errors and the number of accumulated occurrences of bit errors. The present invention is suitable for prevention of bit errors due to read disturb and can recover the bit data which changes with time, and therefore makes it possible to improve the reliability of the flash memory by preventing occurrence of bit errors. ## Claims ### Claim 1 A bit error prevention method of preventing a bit error which is caused by a change of bit data stored in a rewritable nonvolatile semiconductor memory, comprising: a condition judgment step of judging whether a repair condition related to the bit error is satisfied or not when stored data which is stored in said nonvolatile semiconductor memory is read out by a host system; and a recovery step of rewriting said stored data which is read out in said nonvolatile semiconductor memory if said stored data which is read out satisfies said repair condition. ### Claim 2 (depends on 1) The bit error prevention method according to claim 1, wherein said repair condition is conditioned with a threshold value which is set in advance, said condition judgment step includes the step of judging whether a comparison value of said stored data to be read out, corresponding to said threshold value, exceeds said threshold value or not, and said recovery step includes the step of rewriting said stored data which is read out into said nonvolatile semiconductor memory if said comparison value exceeds the threshold value. ### Claim 3 (depends on 2) The bit error prevention method according to claim 2, further comprising the step of storing said stored data into a temporary memory part as temporarily stored data in response to a read request from said host system, wherein it is judged whether or not said comparison value exceeds said threshold value when said temporarily stored data is stored into said temporary memory part, and if said comparison value exceeds said threshold value, said temporarily stored data is rewritten into said nonvolatile semiconductor memory. ### Claim 4 (depends on 3) The bit error prevention method according to claim 3, further comprising an error correction step of judging whether or not said temporarily stored data has an error when said temporarily stored data is stored into said temporary memory part and correcting the error in said temporarily stored data if said temporarily stored data has an error, wherein said temporarily stored data with its error corrected is rewritten into said nonvolatile semiconductor memory. ### Claim 5 (depends on 2) The bit error prevention method according to claim 2, wherein said threshold value includes at least one of the number of readouts of said stored data, the number of bit errors included in said stored data which is read out or the number of accumulated occurrences of bit errors in said stored data which is read out. ### Claim 6 (depends on 1) The bit error prevention method according to claim 1, further comprising a reading step of making read access to a memory area of said nonvolatile semiconductor memory which stores said stored data at a predetermined timing. ### Claim 7 (depends on 6) The bit error prevention method according to claim 6, wherein said predetermined timing includes power-on or power-off. ### Claim 8 (depends on 6) The bit error prevention method according to claim 6, wherein read access is made to entire memory area or part of memory area in said nonvolatile semiconductor memory in said reading step. ### Claim 9 (depends on 1) The bit error prevention method according to claim 1, wherein said bit error includes a read disturb error. ### Claim 10 An information processing apparatus, comprising: a rewritable nonvolatile semiconductor memory; a read part for reading stored data which is stored in said nonvolatile semiconductor memory; a condition judgment part for checking if said stored data to be read out by said read part satisfies a repair condition related to a bit error; and a recovery part for rewriting said stored data which is read out into said nonvolatile semiconductor memory if said stored data which is read out satisfies said repair condition. ### Claim 11 (depends on 10) The information processing apparatus according to claim 10, wherein said repair condition is conditioned with a threshold value which is set in advance, said condition judgment part includes a judgment part for judging whether a comparison value of said stored data to be read out, corresponding to said threshold value, exceeds said threshold value or not, and said recovery part includes a rewrite part for rewriting said stored data which is read out into said nonvolatile semiconductor memory if said comparison value exceeds the threshold value. ### Claim 12 (depends on 11) The information processing apparatus according to claim 11, further comprising a temporary memory part for temporarily storing said stored data therein as temporarily stored data in response to a read request from said read part, wherein it is judged whether or not said comparison value exceeds said threshold value when said temporarily stored data is stored into said temporary memory part, and if said comparison value exceeds said threshold value, said temporarily stored data is rewritten into said nonvolatile semiconductor memory. ### Claim 13 (depends on 12) The information processing apparatus according to claim 12, further comprising an error correction part for judging whether or not said temporarily stored data has an error when said temporarily stored data is stored into said temporary memory part and correcting the error in said temporarily stored data if said temporarily stored data has an error, wherein said temporarily stored data with its error corrected is rewritten into said nonvolatile semiconductor memory. ### Claim 14 (depends on 11) The information processing apparatus according to claim 11, wherein said nonvolatile semiconductor memory has a memory area for storing said stored data therein and a redundant area for storing error correction data therein, and said threshold value is set in said redundant area. ### Claim 15 (depends on 14) The information processing apparatus according to claim 14, wherein said memory area is divided into a plurality of element memory areas on the basis of the characteristics on a bit error and said threshold value is set for each of said element memory areas. ### Claim 16 (depends on 11) The information processing apparatus according to claim 11, wherein said threshold value includes at least one of the number of readouts of said stored data, the number of bit errors included in said stored data which is read out or the number of accumulated occurrences of bit errors in said stored data which is read out. ### Claim 17 (depends on 10) The information processing apparatus according to claim 10, further comprising a part for making read access to a memory area of said nonvolatile semiconductor memory which stores said stored data at a predetermined timing. ### Claim 18 (depends on 17) The information processing apparatus according to claim 17, wherein said predetermined timing includes power-on or power-off. ### Claim 19 (depends on 17) The information processing apparatus according to claim 17, wherein said part for making read access makes read access to entire memory area or part of memory area in said nonvolatile semiconductor memory ### Claim 20 (depends on 10) The information processing apparatus according to claim 10, wherein said bit error includes a read disturb error.