# US 2008/0189520 A1 · Using performance data for instruction thread direction > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2008/0189520 A1 - Document ID: US20080189520A1 - Status: Published application - Kind: A1 - Application number: 11/671,627 - Filed: 2007-02-06 - Published: 2008-08-07 - Earliest claimed: 2007-02-06 - Assignees: International Business Machines Corporation - Inventors: Deepak K. Singh; Francois Ibrahim Atallah - Web page: https://patentgrep.com/patent/US20080189520A1 ## CPC - G06F 9/3851: {from multiple instruction streams, e.g. multistreaming} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method for dispatching instructions in the data processing system, having in memory for storing instructions and a plurality of central processing units, where each central processing unit includes a circuit to provide data indicating internal performance, the method having steps of receiving internal performance data signals from a pool of central processing units, selecting a central processing unit according to the received internal performance data and dispatching instructions from the memory to the selected central processing unit. ## Claims ### Claim 1 A method of dispatching instructions in a data processing system having a memory for storing instructions and a plurality of central processing units (CPUs), each CPU providing a signal indicating CPU internal performance data, the method comprising the steps of: receiving internal performance data signals from the plurality of CPUs, selecting a CPU according to the received internal performance data, and dispatching instructions from said memory to the selected CPU. ### Claim 2 (depends on 1) A method according to claim 1, wherein said selecting step includes the step of determining from the received internal performance data signals which of the plurality of CPUs has the highest performance and selecting the CPU with the highest performance. ### Claim 3 (depends on 1) A method according to claim 1, wherein said selecting step includes the step of determining which of the plurality of CPUs is able to receive instructions for execution. ### Claim 4 (depends on 1) A method according to claim 1, wherein said step of receiving internal performance data signals from the plurality of CPUs further includes the steps of: for each CPU, measuring temperature within the circuit to provide a measured temperature, using the measured temperature to access previously stored frequency data indicating a predicted frequency, measuring frequency within the circuit to provide a measured frequency, and combining the predicted frequency with the measured frequency to provide an internal performance data signal. ### Claim 5 (depends on 4) A method according to claim 4 wherein said adjusting a voltage step includes measuring frequency response of the circuit and comparing the result to the accessed previously stored frequency response data. ### Claim 6 (depends on 5) A method according to claim 5 wherein said step of measuring frequency response of the circuit includes receiving a signal from a ring oscillator contained on the circuit. ### Claim 7 (depends on 6) A method according to claim 6 wherein said adjusting voltage step includes increasing the voltage in response to the measured frequency response being higher than the accessed previously stored frequency response data or decreasing the voltage in response to the measured frequency response being lower than the accessed previously stored frequency response data. ### Claim 8 (depends on 6) A method according to claim 6 wherein said adjusting voltage step includes receiving data from a programmable register and selectively adjusting the voltage in response to either the data from the programmable register or in response to the accessed previously stored frequency response data. ### Claim 9 A data processing system comprising: a plurality of central processing units (CPUs) where each CPU having an internal performance measurement circuit providing an internal performance data signal, a memory including program instructions for execution by a CPU and connected to said plurality of CPUs, a selection circuit connected to the plurality of CPUs to receive internal performance data signals and providing a signal indicating a selected CPU, and an instruction dispatching circuit connected to the memory and the plurality of CPUs and providing instructions to the selected CPU. ### Claim 10 (depends on 9) A data processing system according to claim 9 wherein said selection circuit includes a circuit for receiving the plurality of internal performance signals from the CPUs and providing the selected CPU signal for the CPU having the highest internal performance. ### Claim 11 (depends on 9) A data processing system according to claim 9 wherein said selection circuit includes a circuit to determine which of the plurality of CPUs are idle and is able to receive instructions for execution. ### Claim 12 A computer program product stored in a computer operable media, the computer operable media containing instructions for execution by a computer, which, when executed by the computer, cause the computer to implement a method for dispatching instructions in a data processing system having a memory for storing instructions and a plurality of central processing units (CPUs), each CPU providing a signal indicating CPU internal performance data, the method comprising the steps of: receiving internal performance data signals from the plurality of CPUs, selecting a CPU according to the received internal performance data, and dispatching instructions from said memory to the selected CPU. ### Claim 13 (depends on 12) The computer program product of claim 12, wherein said selecting step includes the step of determining from the received internal performance data signals which of the plurality of CPUs has the highest performance and selecting the CPU with the highest performance. ### Claim 14 (depends on 12) The computer program product of claim 12, wherein said selecting step includes the step of determining which of the plurality of CPUs is able to receive instructions for execution. ### Claim 15 (depends on 12) The computer program product of claim 12, wherein said step of receiving internal performance data signals from the plurality of CPUs further includes the steps of: for each CPU, measuring temperature within the circuit to provide a measured temperature, using the measured temperature to access previously stored frequency data indicating a predicted frequency, measuring frequency within the circuit to provide a measured frequency, and combining the predicted frequency with the measured frequency to provide an internal performance data signal. ### Claim 16 (depends on 16) The computer program product of claim 16 wherein said adjusting a voltage step includes measuring frequency response of the circuit and comparing the result to the accessed previously stored frequency response data. ### Claim 17 (depends on 16) The computer program product of claim 16 wherein said step of measuring frequency response of the circuit includes receiving a signal from a ring oscillator contained on the circuit. ### Claim 18 (depends on 17) The computer program product of claim 17 wherein said adjusting voltage step includes increasing the voltage in response to the measured frequency response being higher than the accessed previously stored frequency response data or decreasing the voltage in response to the measured frequency response being lower than the accessed previously stored frequency response data. ### Claim 19 (depends on 17) The computer program product of claim 17 wherein said adjusting voltage step includes receiving data from a programmable register and selectively adjusting the voltage in response to either the data from the programmable register or in response to the accessed previously stored frequency response data.