# US 2008/0189518 A1 · Processor instruction cache with dual-read modes

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- Number: US 2008/0189518 A1
- Document ID: US20080189518A1
- Status: Published application
- Kind: A1
- Application number: 12/061,296
- Filed: 2008-04-02
- Published: 2008-08-07
- Earliest claimed: 2006-10-13
- Assignees: Marvell World Trade Ltd.
- Inventors: Sehat Sutardja; Jason T. Su; Hong-Yi Chen; Jason Sheu; Jensen Tjeng
- Web page: https://patentgrep.com/patent/US20080189518A1

## CPC

- G06F 12/0882: Page mode
- G06F 9/30054: {Unconditional branch instructions}
- G06F 9/30058: {Conditional branch instructions}
- G06F 9/3804: {for branches, e.g. hedging, branch folding}
- G06F 9/3844: {using dynamic branch prediction, e.g. using branch history tables}
- G11C 7/1018: {Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters}
- G11C 7/1051: {Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits}
- G11C 7/106: {Data output latches}
- G11C 7/1078: {Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits}
- G11C 7/1087: {Data input latches}
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 7/06: Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits}
- G11C 2207/2245: Memory devices with an internal cache buffer
- G11C 2207/2281: Timing of a read operation
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A processor includes a cache memory that has an array, word lines, and bit lines. A control module accesses cells of the array during access cycles to access instructions stored in the cache memory. The control module performs one of a first discrete read and a first sequential read to access instructions in a first set of cells of the array that are connected to a first word line and selectively performs one of a second discrete read and a second sequential read based on a branch instruction to access instructions in a second set of cells of the array that are connected to a second word line. The second word line is different than the first word line.

## Claims

### Claim 1

A processor comprising:
a cache memory that comprises:
an array;
word lines; and
bit lines; and
a control module that accesses cells of said array during access cycles to access instructions stored in said cache memory,
wherein said control module selectively performs one of a first sequential read and a first discrete read to access instructions in a first set of cells of said array that are connected to a first word line and that selectively performs one of a second sequential read and a second discrete read based on a first branch instruction to access instructions in a second set of cells of said array that are connected to a second word line, and
wherein said second word line is different than said first word line.

### Claim 2 (depends on 1)

The processor of claim 1 wherein said control module, when performing said first sequential read, enables said first word line of said cache memory to access a first cell in said first word line, disables said first word line, and maintains said first word line in a disabled state when accessing a second cell in said first word line.

### Claim 3 (depends on 1)

The processor of claim 1 wherein said control module, when performing said first sequential read, generates a first word line pulse associated with said first word line for a first access cycle of said bit lines and selectively refrains from generating a second word line pulse for said first word line for a second access cycle of said bit lines.

### Claim 4 (depends on 1)

The processor of claim 1 wherein said control module determines bit line separation based on a number of said access cycles to be performed along a first word line, and
wherein said control module precharges said bit lines connected to said first word line to provide said bit line separation when accessing said first set of cells.

### Claim 5 (depends on 4)

The processor of claim 4 wherein said control module precharges a set of said bit lines connected to said first word line to provide said bit line separation when accessing a first set of cells of said array, and
wherein said control module selectively refrains from precharging at least one of said set of said bit lines when accessing a second set of cells of said array based on connections between said second set of cells and said first word line.

### Claim 6 (depends on 5)

The processor of claim 5 wherein said control module refrains from precharging said at least one of said set of said bit lines when said second set of cells is connected to said first word line.

### Claim 7 (depends on 5)

The processor of claim 5 wherein said control module precharges said at least one of said set of bit lines when said second set of cells is connected to a word line other than said first word line.

### Claim 8 (depends on 1)

The processor of claim 1 wherein said control module adjusts precharge timing of said bit lines based on a rate of a clock signal.

### Claim 9 (depends on 1)

The processor of claim 1 wherein said control module delays precharging of said bit lines when a rate of a clock signal is less than a predetermined rate.

### Claim 10 (depends on 1)

The processor of claim 1 wherein said control module selectively operates in a discrete read mode and a sequential read mode.

### Claim 11 (depends on 1)

The processor of claim 1 wherein said control module generates a sequential read signal to enable a sequential read mode and generates a word line signal based on said sequential read signal.

### Claim 12 (depends on 1)

The processor of claim 1 wherein said control module generates a sequential read signal to enable a sequential read mode and precharges said bit lines based on said sequential read signal.

### Claim 13 (depends on 1)

The processor of claim 1 wherein said control module, when in a discrete mode, performs row address decoding, word line enablement, and bit line precharging for each access of each of said cells.

### Claim 14 (depends on 1)

The processor of claim 1 wherein said control module, when accessing cells in a first mode, precharges said bit lines and performs row address decoding for each read cycle, and
wherein said control module, when accessing cells in a second mode, precharges said bit lines, performs row address decoding for a first read cycle, does not precharge said bit lines, and does not perform row address decoding for a second read cycle.

### Claim 15 (depends on 1)

The processor of claim 1 further comprising a column decoder that selects cells of said array via a column select signal, wherein said control module generates a latch signal to latch bit information in said selected cells based on said column select signal.

### Claim 16 (depends on 1)

The processor of claim 1 further comprising an amplification module that detects and amplifies bit information in said first and second set of cells.

### Claim 17 (depends on 1)

The processor of claim 1 further comprising a row decoder, wherein said control module generates a word line signal via said row decoder to access said first set of cells.

### Claim 18 (depends on 17)

The processor of claim 17 wherein said word line signal defines an extended period to increase said bit line separation.

### Claim 19 (depends on 18)

The processor of claim 18 wherein said extended period increases bit line separation time and sets said bit line separation at a predetermined voltage.

### Claim 20 (depends on 18)

The processor of claim 18 wherein said extended period is based on a predetermined number of read cycles.

### Claim 21 (depends on 1)

The processor of claim 1 further comprising a column decoder, wherein said control module generates bit line signals via said column decoder to access said first set of cells.

### Claim 22 (depends on 1)

The processor of claim 1 further comprising a sense-amplifier that has a plurality of common lines and that receives a precharge signal to precharge said common lines before latching bit information in said first and second set of cells.

### Claim 23 (depends on 1)

The processor of claim 1 wherein said control module precharges said bit lines based on a precharge flag that indicates when a precharge has been performed.

### Claim 24 (depends on 1)

The processor of claim 1 wherein said control module precharges said bit lines based on timing of a previous precharge of said bit lines.

### Claim 25 (depends on 1)

The processor of claim 1 wherein said control module, when performing said second sequential read, enables said second word line of said cache memory to access a cell in said second word line, disables said second word line, and maintains said second word line in a disabled state when accessing another cell in said second word line.

### Claim 26 (depends on 1)

The processor of claim 1 wherein said control module performs in a discrete read mode based on said first branch instruction.

### Claim 27

A method comprising:
providing a cache memory that comprises:
an array of cells;
word lines; and
bit lines;
accessing cells of said array during access cycles to access instructions stored in said cache memory;
performing one of a first discrete read and a first sequential read to access instructions in a first set of cells of said array that are connected to a first word line; and
selectively performing one of a second discrete read and a second sequential read based on a first branch instruction to access instructions in a second set of cells of said array that are connected to a second word line,
wherein said second word line is different than said first word line.

### Claim 28 (depends on 27)

The method of claim 27 further comprising, when performing said first sequential read, enabling said first word line of said cache memory to access a first cell in said first word line, disabling said first word line, and maintaining said first word line in a disabled state when accessing a second cell in said first word line.

### Claim 29 (depends on 27)

The method of claim 27 further comprising, when performing said first sequential read, generates a first word line pulse associated with said first word line for a first access cycle of said bit lines and selectively refrains from generating a second word line pulse for said first word line for a second access cycle of said bit lines.

### Claim 30 (depends on 27)

The method of claim 27 further comprising:
determining bit line separation based on a number of said access cycles to be performed along a first word line; and
precharging said bit lines connected to said first word line to provide said bit line separation when accessing said first set of cells.

### Claim 31 (depends on 30)

The method of claim 30 further comprising:
precharging a set of said bit lines connected to said first word line to provide said bit line separation when accessing a first set of cells of said array; and
selectively refraining from precharging at least one of said set of said bit lines when accessing a second set of cells of said array based on connections between said second set of cells and said first word line.

### Claim 32 (depends on 31)

The method of claim 31 further comprising refraining from precharging said at least one of said set of said bit lines when said second set of cells is connected to said first word line.

### Claim 33 (depends on 31)

The method of claim 31 further comprising precharging said at least one of said set of bit lines when said second set of cells is connected to a word line other than said first word line.

### Claim 34 (depends on 27)

The method of claim 27 further comprising adjusting precharge timing of said bit lines based on a rate of a clock signal.

### Claim 35 (depends on 27)

The method of claim 27 further comprising delaying precharging of said bit lines when a rate of a clock signal is less than a predetermined rate.

### Claim 36 (depends on 27)

The method of claim 27 further comprising selectively operating in a discrete read mode and a sequential read mode.

### Claim 37 (depends on 27)

The method of claim 27 further comprising generating a sequential read signal to enable a sequential read mode and generating a word line signal based on said sequential read signal.

### Claim 38 (depends on 27)

The method of claim 27 further comprising generating a sequential read signal to enable a sequential read mode and precharging said bit lines based on said sequential read signal.

### Claim 39 (depends on 27)

The method of claim 27 further comprising, when in a discrete mode, performing row address decoding, word line enablement, and bit line precharging for each access of each of said cells.

### Claim 40 (depends on 27)

The method of claim 27 further comprising:
when accessing cells in a first mode, precharging said bit lines and performing row address decoding for each read cycle; and
when accessing cells in a second mode, precharging said bit lines, performing row address decoding for a first read cycle, refraining from precharging said bit lines, and refraining from performing row address decoding for a second read cycle.

### Claim 41 (depends on 27)

The method of claim 27 further comprising:
selecting cells of said array via a column select signal, and
generating a latch signal to latch bit information in said selected cells based on said column select signal.

### Claim 42 (depends on 27)

The method of claim 27 further comprising detecting and amplifying bit information in said first and second set of cells.

### Claim 43 (depends on 27)

The method of claim 27 further comprising generating a word line signal via said row decoder to access said first set of cells.

### Claim 44 (depends on 43)

The method of claim 43 wherein said word line signal defines an extended period to increase said bit line separation.

### Claim 45 (depends on 44)

The method of claim 44 wherein said extended period increases bit line separation time and sets said bit line separation at a predetermined voltage.

### Claim 46 (depends on 44)

The method of claim 44 wherein said extended period is based on a predetermined number of read cycles.

### Claim 47 (depends on 27)

The method of claim 27 further comprising generating bit line signals via said column decoder to access said first set of cells.

### Claim 48 (depends on 27)

The method of claim 27 further comprising receiving a precharge signal to precharge common lines of a sense-amplifier before latching bit information in said first and second set of cells.

### Claim 49 (depends on 27)

The method of claim 27 further comprising precharging said bit lines based on a precharge flag that indicates when a precharge has been performed.

### Claim 50 (depends on 27)

The method of claim 27 further comprising precharging said bit lines based on timing of a previous precharge of said bit lines.

### Claim 51 (depends on 27)

The method of claim 27 further comprising, when performing said second sequential read, enabling said second word line of said cache memory to access a cell in said second word line, disabling said second word line, and maintaining said second word line in a disabled state when accessing another cell in said second word line.

### Claim 52 (depends on 27)

The method of claim 27 further comprising performing in a discrete read mode based on said first branch instruction.

### Claim 53 (depends on 1)

The processor of claim 1 wherein said processor pre-fetches and decodes subsequent instructions in a pipeline and further comprising a branch prediction module that predicts whether one of said subsequent instructions that is a second branch instruction is likely to be taken.

### Claim 54 (depends on 53)

The processor of claim 53 wherein said branch prediction module selectively performs one of a discrete read and a sequential read on said branch instruction based on said prediction and on whether said branch instruction involves multiple reads along a same word line.

### Claim 55 (depends on 54)

The processor of claim 54 wherein said branch prediction module includes a branch history module that outputs branch prediction data based on an address of said second branch instruction and wherein said branch prediction module bases said prediction on said branch prediction data.

### Claim 56 (depends on 27)

The method of claim 27 further comprising:
pre-fetching and decoding subsequent instructions in a pipeline;
predicting whether one of said subsequent instructions that is a second branch instruction is likely to be taken.

### Claim 57 (depends on 56)

The method of claim 56 further comprising:
selectively performing one of a discrete read and a sequential read on said branch instruction based on said prediction and on whether said branch instruction involves multiple reads along a same word line.

### Claim 58 (depends on 57)

The method of claim 57 further comprising:
generating branch prediction data based on an address of said second branch instruction; and
basing said prediction on said branch prediction data.