# US 2008/0189489 A1 · Regularly occurring write back scheme for cache soft error reduction > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2008/0189489 A1 - Document ID: US20080189489A1 - Status: Published application - Kind: A1 - Application number: 11/670,381 - Filed: 2007-02-01 - Published: 2008-08-07 - Earliest claimed: 2007-02-01 - Assignees: Cisco Technology, Inc. - Inventors: Somnath Mitra - Web page: https://patentgrep.com/patent/US20080189489A1 ## CPC - G06F 12/0804: with main memory updating (G06F12/0806 takes precedence) - G06F 12/123: with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list - G06F 12/127: using additional replacement algorithms - G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract In one embodiment, a processor regularly writes one or more cache entries back to memory to reduce the likelihood of cache soft errors. The regularly occurring write backs operate independently of Least Recently Used (LRU) status of the entries so that all entries are flushed. ## Claims ### Claim 1 A method, comprising: selecting one or more cache entries to be written to a remote memory at a first occurrence of a regularly occurring time interval, said selecting occurring independently of how recently the identified cache entries have been used; and writing the cache entries to the remote memory at the first occurrence of the regularly occurring time interval. ### Claim 2 (depends on 1) The method of claim 1 wherein the cache entries are selected independently of a Least Recently Used (LRU) status of the cache entries. ### Claim 3 (depends on 1) The method of claim 1 further comprising: selecting a next cache line to be written to the remote memory at a second next occurrence of the regularly occurring time interval, the next cache line selected according to physical proximity of a region in the cache that corresponds to the next cache line and a different region in a cache that corresponds to the cache entries; and writing the next cache line to the remote memory at the next regularly occurring time interval. ### Claim 4 (depends on 1) The method of claim 1 wherein said selecting occurs independently of how long the selected entries have been marked as dirty. ### Claim 5 (depends on 1) The method of claim 1 the selected entries comprise all ways in one or more indexes. ### Claim 6 (depends on 1) The method of claim 1 wherein the cache is integrated with one or more processors controlling the selection and the memory is non-integrated with the processors. ### Claim 7 (depends on 1) The method of claim 1 wherein an amount of the cache entries are selected so that the entire cache is written back after sixty four occurrences of the regularly occurring time interval. ### Claim 8 (depends on 1) The method of claim 1 further comprising: systematically continuing to write remaining cache entries to memory according to the regularly occurring time interval such that the entire cache is flushed without regard to Least Recently Used (LRU) status; and repeatedly re-flushing the cache by writing back all the cache entries to memory in a same order as the previous flushing. ### Claim 9 (depends on 1) The method of claim 1 wherein the regularly occurring time interval occurs periodically and has a period of 400 μs. ### Claim 10 (depends on 1) The method of claim 1 further comprising intermittently writing back data to the remote memory whenever a dirty cache entry is identified for rewriting. ### Claim 11 An apparatus comprising: one or more processors; and a memory coupled to the processors comprising instructions executable by the processors, the processor operable when executing the instructions to: perform unscheduled write backs of data stored in a cache in response to observing that the data is dirty and selected for write-over; receive a regularly occurring timing signal; and perform scheduled write backs of cache entries to memory whenever the timing signal is received regardless of how often the cache entries are accessed until data stored on the cache is fully backed up to a memory. ### Claim 12 (depends on 11) The apparatus of claim 11 wherein the scheduled write backs backup a repetitively read cache entry that is not selected for write-over and not written back during the unscheduled write backs thereby reducing a likelihood of a soft error occurring in the repetitively read cache entry. ### Claim 13 (depends on 11) The apparatus of claim 11 wherein the scheduled write backs occur regardless of whether the cache entries are marked as dirty. ### Claim 14 (depends on 11) The apparatus of claim 11 wherein the processor is further operable to constantly repeat the scheduled write backs. ### Claim 15 (depends on 14) The apparatus of claim 14 wherein the cache entries are written back in a same order during the constantly repeated scheduled write backs. ### Claim 16 (depends on 15) The apparatus of claim 15 wherein the order is chosen according to a physical arrangement of cache lines that store the cache entries. ### Claim 17 An apparatus comprising: means for performing a first type of write backs from a cache to a memory, the first type of write backs initiated in association with one or more processors writing to the cache; means for generating a triggering signal, the generation of the triggering signal being unassociated with the processors writing to either the cache or the memory during the first type of write backs; and means for performing a second type of write backs from the cache to the memory, the second type of write backs initiated in response to the triggering signal. ### Claim 18 (depends on 17) The apparatus of claim 17 wherein the triggering signal is periodic. ### Claim 19 (depends on 17) The apparatus of claim 17 wherein the second type of write backs are configured to write back all cache lines in the cache to the memory in a predetermined amount of time independently of how frequently the processors write new data to the cache. ### Claim 20 (depends on 17) The apparatus of claim 17 wherein the second type of write backs repeat constantly using a same order of cache lines.