# US 2008/0189474 A1 · Memory card and memory system having the same

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- Number: US 2008/0189474 A1
- Document ID: US20080189474A1
- Status: Published application
- Kind: A1
- Application number: 11/761,620
- Filed: 2007-06-12
- Published: 2008-08-07
- Earliest claimed: 2007-02-06
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Ki-Hong Kim; Byeong-Hoon Lee; Seung-Won Lee; Sun-Kwon Kim
- Web page: https://patentgrep.com/patent/US20080189474A1

## CPC

- G11C 16/20: Initialising; Data preset; Chip identification
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory card includes: a first memory chip responding to all commands input externally; and a second memory chip responding to commands, among the commands input externally, relevant to reading, programming, and erasing operations with data. Card identification information stored in the first memory chip includes capacity information corresponding to a sum of sizes of the first and second memory chips. The plurality of memory chips of the memory card are useful in designing the memory card with storage capacity in various forms.

## Claims

### Claim 1

A memory card comprising:
a first memory chip responding to all commands input externally; and
a second memory chip responding to commands, among the commands input externally, relevant to reading, programming, and erasing operations with data,
wherein card identification information stored in the first memory chip includes capacity information corresponding to a sum of sizes of the first and second memory chips.

### Claim 2 (depends on 1)

The memory card as set forth in claim 1, wherein the second memory chip stores the same card identification information with the first memory chip.

### Claim 3 (depends on 2)

The memory card as set forth in claim 2, wherein the first memory chip comprises:
a first flash memory; and
a first controller operating to control the first flash memory.

### Claim 4 (depends on 3)

The memory card as set forth in claim 3, wherein the first flash memory comprises:
a memory cell array; and
a peripheral block configured to control reading, programming, and erasing operations of the memory cell array by the first controller.

### Claim 5 (depends on 4)

The memory card as set forth in claim 4, wherein the memory cell array of the first flash memory stores the card identification information.

### Claim 6 (depends on 5)

The memory card as set forth in claim 5, wherein the first controller comprises a register for storing the card identification information read out by the peripheral block at a power-up time.

### Claim 7 (depends on 6)

The memory card as set forth in claim 6, wherein the first controller of the first memory chip outputs the card identification information externally of the memory card in response to a command input externally.

### Claim 8 (depends on 4)

The memory card as set forth in claim 4, wherein the memory card is a multimedia card.

### Claim 9 (depends on 8)

The memory card as set forth in claim 8, wherein the first controller comprises:
a CPU;
a host interface configured to communicate externally in a multimedia card interface mode under control of the CPU;
a flash interface configured to control the peripheral block under control of the CPU; and
a buffer RAM connected between the host interface and a flash interface and configured to temporarily store transmission data.

### Claim 10 (depends on 2)

The memory card as set forth in claim 2, wherein the second memory chip comprises:
a second flash memory; and
a second controller operating to control the second flash memory.

### Claim 11 (depends on 10)

The memory card as set forth in claim 10, wherein the second flash memory comprises:
a memory cell array; and
a peripheral block configured to control reading, programming, and erasing operations of the memory cell array by the second controller.

### Claim 12 (depends on 11)

The memory card as set forth in claim 11, wherein the memory cell array of the second flash memory stores the card identification information.

### Claim 13 (depends on 12)

The memory card as set forth in claim 12, wherein the second controller of the second memory chip comprises a register for storing the card identification information read out by the peripheral block at a power-up time.

### Claim 14 (depends on 10)

The memory card as set forth in claim 10, wherein the second controller comprises:
a CPU;
a host interface configured to communicate externally in a multimedia card interface mode under control by the CPU;
a flash interface configured to control the peripheral block under control by the CPU; and
a buffer RAM connected between the host interface and flash interface and configured to temporarily store transmission data.

### Claim 15

A memory system comprising:
a host; and
a multimedia card configured to communicate with the host,
wherein the multimedia card comprises:
a first memory chip responding to ail commands input from the host; and
a second memory chip responding to commands, among the commands input from the host, relevant to writing and reading operations with data.
wherein card identification information stored in the first memory chip includes capacity information corresponding to a sum of sizes of the first and second memory chips.

### Claim 16 (depends on 15)

The memory system as set forth in claim 15, wherein the second memory chip stores the same card identification information as the first memory chip.

### Claim 17 (depends on 16)

The memory system as set forth in claim 16, wherein each of the first and second memory chips comprises:
a flash memory; and
a controller operating to control the flash memory.

### Claim 18 (depends on 17)

The memory system as set forth in claim 17, wherein the flash memory comprises:
a memory cell array; and
a peripheral block configured to control reading, programming, and erasing operations of the memory cell array by the controller.

### Claim 19 (depends on 18)

The memory system as set forth in claim 18, wherein the memory cell array stores the card identification information.

### Claim 20 (depends on 19)

The memory system as set forth in claim 19, wherein the controller comprises a register for storing the card identification information read out by the peripheral block at a power-up time.

### Claim 21 (depends on 20)

The memory system as set forth in claim 20, wherein the host provides the multimedia card with a command for reading the card identification information in a card identification mode and the first memory chip of the multimedia card outputs the card identification information to the host in response to the read command provided from the host.

### Claim 22 (depends on 15)

The memory system as set forth in claim 15, wherein the controller comprises a ROM storing firmware to control the flash memory.

### Claim 23 (depends on 15)

The memory system as set forth in claim 15, wherein the host provides the multimedia card with an address while accessing the multimedia card.

### Claim 24 (depends on 23)

The memory system as set forth in claim 23, wherein the controller operates to control access to a memory cell array corresponding to the address if the address provided from the host belongs to a first address group.

### Claim 25 (depends on 24)

The memory system as set forth in claim 24, wherein the controller operates to control access to a memory cell array corresponding to the address if the address provided from the host belongs to a second address group.

### Claim 26 (depends on 25)

The memory system as set forth in claim 25, wherein the first address group includes odd-ordered addresses and the second address group includes even-ordered addresses.

### Claim 27

A method of operating a memory system having a host and a multimedia card including first and second memory chips, the method comprising:
connecting the multimedia card to the host;
transferring card identification information to the host from the first memory chip of the multimedia card; and
executing a reading, programming, or erasing operation of the first or/and second memory chips under control by the host,
wherein card identification information stored in the first memory chip includes capacity information corresponding to a sum of sizes of the first and second memory chips.

### Claim 28 (depends on 27)

The method as set forth in claim 27, the second memory chip stores the same card identification information as the first memory chip.

### Claim 29 (depends on 27)

The method as set forth in claim 27, wherein each of the first and second memory chips is a flash memory chip.

### Claim 30 (depends on 27)

The method as set forth in claim 27, further comprising: providing the flash memory with an address provided from the host.

### Claim 31 (depends on 30)

The method as set forth in claim 30, wherein the first memory chip executes the reading, programming, or erasing operation if the address provided from the host belongs to a first address group.

### Claim 32 (depends on 31)

The method as set forth in claim 31, wherein the second memory chip executes the reading, programming, or erasing operation if the address provided from the host belongs to a second address group.

### Claim 33 (depends on 32)

The method as set forth in claim 32, wherein the first address group includes odd-ordered addresses and the second address group includes even-ordered addresses.

### Claim 34

A memory system comprising:
a host; and
a multimedia card bus coupled to the host,
a first multimedia card communicating with the host through the multimedia card bus and responding to all commands input from the host; and
a second multimedia card responding to commands, among the commands input from the host, relevant to writing and reading operations with data and communicating with the host through the multimedia card bus,
wherein card identification information stored in the first multimedia card includes capacity information corresponding to a sum of sizes of the first and second multimedia cards.

### Claim 35 (depends on 34)

The memory system as set forth in claim 34, wherein the second multimedia card stores the same card identification information as the first multimedia card.

### Claim 36 (depends on 35)

The memory system as set forth in claim 35, wherein each of the first and second multimedia cards comprises:
a flash memory; and
a controller operating to control the flash memory.