# US 2008/0188092 A1 · Electronic Device Array > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2008/0188092 A1 - Document ID: US20080188092A1 - Status: Published application - Kind: A1 - Application number: 11/793,294 - Filed: 2005-12-16 - Published: 2008-08-07 - Earliest claimed: 2004-12-16 - Assignees: Plastic Logic Limited - Inventors: Paul A. Cain - Web page: https://patentgrep.com/patent/US20080188092A1 ## CPC - H10K 19/10: comprising field-effect transistors - H10K 71/231: {by etching of existing layers} - H10K 10/462: {Insulated gate field-effect transistors [IGFETs]} - H10K 10/464: {Lateral top-gate IGFETs comprising only a single gate} - H10K 10/468: {characterised by the gate dielectrics} - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES ## Abstract A method of producing an array of electronic devices, the method including the steps of: forming one or more first conductive elements of a first electronic device on a substrate and one or more second conductive elements of a second electronic device on said substrate; and forming a layer of channel material over the substrate and the first and second conductive elements to provide a first channel for, in use, the movement of charge carriers between conductive elements of said first electronic device and a second channel for, in use, the movement of charge carriers between conductive elements of said second electronic device; wherein the method also includes the step (a) of using an irradiative technique to decrease in a single step the conductivity of one or more selected portions of the layer of channel material in one or more regions between the first and second conductive elements. ## Claims ### Claim 1 A method of producing an array of electronic devices, the method including the steps of: forming one or more first conductive elements of a first electronic device on a substrate and one or more second conductive elements of a second electronic device on said substrate; and forming a layer of channel material over the substrate and the first and second conductive elements to provide a first channel for, in use, the movement of charge carriers between conductive elements of said first electronic device and a second channel for, in use, the movement of charge carriers between conductive elements of said second electronic device; wherein the method also includes the step (a) of using an irradiative technique to decrease in a single step the conductivity of one or more selected portions of the layer of channel material in one or more regions between the first and second conductive elements. ### Claim 2 (depends on 1) A method according to claim 1, wherein step (a) includes using an irradiative technique to remove in a single step said one or more selected portions of the layer of channel material to thereby reduce the conductivity of said one or more selected portions. ### Claim 3 (depends on 2) A method according to claim 2, wherein step (a) is carried out without irradiating any portions of the layer of channel material overlying the first and second conductive elements. ### Claim 4 A method according to any preceding claim, wherein the channel material is a semiconductor material. ### Claim 5 (depends on 1) A method according to claim 1, wherein step (a) includes using said irradiative technique to locally generate heat in the one or more selected portions of the layer of channel material in between first and second conductive elements and/or respective portions of the substrate underlying said one or more selected portions of the layer of channel material, wherein said heat induces a photothermal and/or photochemical denaturing process of the channel material and acts to reduce the conductivity of said one or more selected portions of the layer of channel material. ### Claim 6 A method according to any preceding claim wherein said step (a) involves ablating said portions of the channel material. ### Claim 7 (depends on 6) A method according to claim 6 wherein the step of ablating said portions of the channel material uses ultraviolet laser radiation. ### Claim 8 (depends on 1) A method according to claim 1, wherein said one or more selected portions in step (a) include one or more lines extending substantially perpendicular to a direction between said first and second conductive elements. ### Claim 9 (depends on 1) A method according to claim 1, wherein the method includes forming a pair of first conductive elements and a pair of second conductive elements on the substrate; and wherein the layer of channel material provides said first channel between said pair of first conductive elements, and said second channel between said pair of second conductive elements. ### Claim 10 (depends on 9) A method according to claim 9, wherein the region in which said selected portions of said layer of channel material are spaced more than 10 micrometers from said first and second channels. ### Claim 11 (depends on 9) A method according to claim 9, wherein said selected portions of said layer of channel material are spaced more than 50 micrometers from said first and second channels. ### Claim 12 (depends on 9) A method according to claim 9, wherein said selected portions of said layer of channel material are spaced more than 10 micrometers from said first and second conductive elements. ### Claim 13 (depends on 9) A method according to claim 9, wherein the region in which said selected portions of said channel material are spaced more than 50 micrometers from said first and second conductive elements. ### Claim 14 (depends on 9) A method according to claim 9, wherein the first pair of conductive elements forms the source and drain electrodes of a first field effect transistor device, and the second pair of conductive elements forms the source and drain electrodes of a second field effect transistor device. ### Claim 15 (depends on 1) A method according to claim 1, wherein said one or more selected portions in step (a) include a series of at least two lines extending continuously under a gate line. ### Claim 16 (depends on 14) A method according to claim 14, further including the steps of (b) forming a dielectric layer over the substrate, the first and second conductive elements and the layer of channel material; and (c) forming a gate line extending over each of the first and second channels. ### Claim 17 (depends on 16) A method according to claim 16, wherein the first and second electronic devices are normally-off field effect transistor devices, and wherein said one or more selected portions of step (a) include portions underlying said gate line. ### Claim 18 (depends on 16) A method according to claim 16, wherein said gate line has a width, and the one or more selected portions of step (a) include one or more lines extending at least the width of said gate line. ### Claim 19 (depends on 16) A method according to claim 16, wherein the first and second electronic devices are normally-on field effect transistor devices, wherein said one or more selected portions of step (a) include (i) portions underlying said gate line and (ii) portions not underlying said gate line. ### Claim 20 (depends on 19) A method according to claim 19, wherein the one or more first conductive elements include a pixel electrode having a number of sides, and wherein the one or more selected portions in step (a) include one or more lines extending along each of the sides of the pixel electrode. ### Claim 21 A method according to any preceding claim, wherein step (a) includes focussing one or more laser beams to one or more points located in said one more selected portions of the layer of channel material or respective portions of the substrate underlying said one or more selected portions. ### Claim 22 A method according to any preceding claim wherein the region of the substrate in which the channel material is irradiated does not form a closed path around the first and/or second electronic device. ### Claim 23 (depends on 5) A method according to any preceding claim as dependant on claim 5, wherein said step of ablating the channel material also ablates a portion of the material of the substrate. ### Claim 24 An array of electronic devices comprising at least one first and one second electronic device on a substrate, each of the first and second electronic devices including a patterned layer of channel material, wherein said patterned layer of channel material also defines, in use, one or more conduction paths between the first and second electronic devices, but wherein the pattern of said layer of channel material is configured such that the shortest conduction path between said first and second electronic devices, is longer by a factor of at least 50% than the shortest physical distance between said first and second electronic devices. ### Claim 25 An array of electronic devices comprising at least one first and one second electronic device on a substrate, each of said first and second electronic devices including a patterned layer of channel material; and the first electronic device including a gate electrode that overlies at least a portion of said patterned layer of channel material and also extends over a portion of the second electronic device; wherein the patterned layer of channel material defines, in use, one or more conduction paths between said first and second electronic devices, but wherein at least a portion of each of said one or more conduction paths runs through a region of said patterned layer of channel material over which said gate electrode is not present. ### Claim 26 (depends on 24, 25) An array of electronic devices according to claim 24 or 25, wherein said pattern of channel material is defined by laser ablation of the channel material. ### Claim 27 (depends on 26) An array of electronic devices according to claim 26, wherein said step of laser ablation is carried out without ablating any portions of the layer of channel material overlying conductive elements of said first and second electronic devices which were predefined on the substrate. ### Claim 28 (depends on 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23) An array of electronic devices produced by a method according to any of claims 1 to 23. ### Claim 29 (depends on 28) A display or memory device including an array of electronic devices according to claim 28.