# US 2008/0188091 A1 · Semiconductor device, method for fabricating thereof and method for increasing film stress

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2008/0188091 A1
- Document ID: US20080188091A1
- Status: Published application
- Kind: A1
- Application number: 12/043,905
- Filed: 2008-03-06
- Published: 2008-08-07
- Earliest claimed: 2007-02-02
- Inventors: SHAO-TA HSU; Teng-Chun Tsai; Neng-Kuo Chen; Hsiu-Lien Liao; Cheng-Han Wu; Wen-Han Hung
- Web page: https://patentgrep.com/patent/US20080188091A1

## CPC

- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers}
- H10W 20/095: {by irradiating with electromagnetic or particle radiation (plasma treatment H10W20/096)}
- H10W 20/096: {by contacting with gases, liquids or plasmas}
- H10W 20/097: {by thermally treating}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for forming a semiconductor device is provided. The method comprises steps of providing a substrate having a first-conductive-type transistor and a second-conductive-type transistor formed thereon and then forming a stress layer over the substrate to conformally cover the first-conductive-type transistor and the second-conductive-type transistor. A cap layer is formed on the stress layer over the first-conductive-type transistor. A modification process is performed. The cap layer is removed.

## Claims

### Claim at position 1

1-8. (canceled)

### Claim 9

A method for forming a semiconductor device, comprising:
providing a substrate having a first-conductive-type transistor and a second-conductive-type transistor formed thereon;
forming a stress layer over the substrate to conformally cover the first-conductive-type transistor and the second-conductive-type transistor;
forming a cap layer on the stress layer over the first-conductive-type transistor;
performing a modification process; and
removing the cap layer.

### Claim 10 (depends on 9)

The method of claim 9, wherein the modification process includes a thermal treatment, an ion implantation, a plasma treatment and an oxidation treatment.

### Claim 11 (depends on 10)

The method of claim 10, wherein the thermal treatment comprises a UV curing, a spike annealing, an E-beam annealing, a laser annealing and a UV rapid thermal process.

### Claim 12 (depends on 9)

The method of claim 9, wherein the first-conductive-type transistor is a P-type transistor and the second-conductive-type transistor is an N-type transistor.

### Claim 13 (depends on 12)

The method of claim 12, wherein, after the modification process, the stress layer over the N-type transistor is 5%˜30% decreased in thickness.

### Claim 14 (depends on 12)

The method of claim 12, wherein, after the UV curing, an increment of a tensile stress of the stress layer over the N-type transistor is about 0.5 GPa˜3.0 GPa.

### Claim 15 (depends on 9)

The method of claim 9, wherein a tensile stress of the stress layer is about 0.5 GPa˜1.5 GPa.

### Claim 16 (depends on 9)

The method of claim 9, wherein the first-conductive-type transistor is an N-type transistor and the second-conductive-type transistor is a P-type transistor.

### Claim 17 (depends on 16)

The method of claim 16, wherein, after the modification process, a compressive stress of the stress layer over the P-type transistor is increased.

### Claim 18 (depends on 9)

The method of claim 9, wherein the material of the stress layer is selected from a group consisting of silicon nitride, polysilicon and silicon oxynitride.

### Claim 19 (depends on 9)

The method of claim 9, wherein the stress layer can be served as an etching strop layer or a conductive cap layer.

### Claim 20 (depends on 9)

The method of claim 9, wherein the cap layer includes a photoresist layer.

### Claim 21

A method for increasing a stress of a layer suitable for a stress layer disposing over a substrate, wherein the stress layer conformally covers a P-type transistor and an N-type transistor on the substrate and the stress layer has a continuous interface, the method comprising:
forming a cap layer on the stress layer over the P-type transistor;
performing a modification process to increase a tensile stress of the stress layer over the N-type transistor; and
removing the cap layer.

### Claim 22 (depends on 21)

The method of claim 21, wherein the modification process includes a thermal treatment, an ion implantation, a plasma treatment and an oxidation treatment.

### Claim 23 (depends on 22)

The method of claim 22, wherein the thermal treatment includes a UV curing, a spike annealing, an E-beam annealing, a laser annealing and a UV rapid thermal process.

### Claim 24 (depends on 23)

The method of claim 23, wherein, after the UV curing, the stress layer is 5%˜30% decreased in thickness.

### Claim 25 (depends on 23)

The method of claim 23, wherein, after the UW curing, an increment of a tensile stress of the stress layer over the N-type transistor is about 0.5 GPa˜3.0 GPa.

### Claim 26 (depends on 23)

The method Of claim 23, wherein a wavelength of a UV light used in the UV curing is about 100 nm˜400 nm.

### Claim 27 (depends on 23)

The method of claim 23, wherein the UV curing is performed at a pressure of about 3 mTorr˜500 mTorr.

### Claim 28 (depends on 22)

The method of claim 22, wherein the cap layer includes a photoresist layer.