# US 2008/0188089 A1 · Method for reducing top notching effects in pre-doped gate structures

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- Number: US 2008/0188089 A1
- Document ID: US20080188089A1
- Status: Published application
- Kind: A1
- Application number: 11/671,668
- Filed: 2007-02-06
- Published: 2008-08-07
- Earliest claimed: 2007-02-06
- Assignees: International Business Machines Corporation
- Inventors: Anthony I. Chou; Sadanand V. Deshpande; Renee T. Mo; Shreesh Narasimha; Katsunori Onishi; Dominic Schepis
- Web page: https://patentgrep.com/patent/US20080188089A1

## CPC

- H10P 14/6308: {of Group IV semiconductors}
- H10D 64/01354: {passivation or protection of the electrode, e.g. using re-oxidation}
- H10D 64/01306: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for reducing top notching effects in pre-doped gate structures includes subjecting an etched, pre-doped gate stack structure to a re-oxidation process, the re-oxidation process comprising a radical assisted re-oxidation process so as to result in the formation of an oxide layer over vertical sidewall and horizontal top surfaces of the etched gate stack structure. The resulting oxide layer has a substantially uniform thickness independent of grain boundary orientations of the gate stack structure and independent of the concentration and location of dopant material present therein.

## Claims

### Claim 1

A method for reducing top notching effects in pre-doped gate structures, the method comprising:
subjecting an etched, pre-doped gate stack structure having a height of about 50 nm or less to a re-oxidation process, the re-oxidation process comprising a radical assisted re-oxidation process implemented at a temperature of about 400° C. or less using a slot plane antenna (SPA) plasma processing system as to result in the formation of an oxide layer over vertical sidewall and horizontal top surfaces of the etched gate stack structure;
wherein the oxide layer has a substantially uniform thickness independent of grain boundary orientations of the gate stack structure and independent of the concentration and location of dopant material present therein;
wherein the gate stack structure comprises an NFET device pre-doped with phosphorus at a concentration of about 5×1015 atoms/cm 2 or more.

### Claim at position 2

2-5. (canceled)

### Claim 6

A method of forming a gate stack structure for a semiconductor device, the method comprising:
forming a gate dielectric layer over a semiconductor substrate;
forming a polysilicon gate conductor layer over the gate dielectric layer;
subjecting unmasked regions of the gate conductor layer to an ion implantation of dopant material;
patterning and etching the gate conductor layer and gate dielectric layer so as to form a pre-doped gate stack structure; and
subjecting the gate stack structure to a re-oxidation process, the re-oxidation process comprising a radical assisted re-oxidation process implemented at a temperature of about 400° C. or less using a slot plane antenna (SPA) plasma processing system so as to result in the formation of an oxide layer over vertical sidewall and horizontal top surfaces of the etched gate stack structure;
wherein the oxide layer has a substantially uniform thickness independent of grain boundary orientations of the gate stack structure and independent of the concentration and location of dopant material present therein; and
wherein the gate stack structure comprises an NFET device pre-doped with phosphorus at a concentration of about 5×1015 atoms/cm 2 or more.

### Claim at position 4

7-11. (canceled)