# US 2008/0188070 A1 · Apparatus and method for semiconductor wafer bumping via injection molded solder

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- Number: US 2008/0188070 A1
- Document ID: US20080188070A1
- Status: Published application
- Kind: A1
- Application number: 12/025,845
- Filed: 2008-02-05
- Published: 2008-08-07
- Earliest claimed: 2007-02-05
- Assignees: Suss Microtec Inc
- Inventors: HALE JOHNSON; WILHELM LAPOINTE
- Web page: https://patentgrep.com/patent/US20080188070A1

## CPC

- H05K 3/3478: Application of solder preforms; Transferring prefabricated solder patterns
- B23K 3/0623: {for shaped solder piece feeding, e.g. preforms, bumps, balls, pellets, droplets}
- H10W 72/0112: {Apparatus for manufacturing bump connectors}
- H05K 2203/0113: Female die used for patterning or transferring, e.g. temporary substrate having recessed pattern
- H05K 2203/0338: Transferring metal or conductive material other than a circuit pattern, e.g. bump, solder, printed component
- H10W 72/01204: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/90: Bond pads, in general
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- B23K: SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An improved apparatus for positioning and aligning a patterned surface of a semiconductor structure directly opposite to solder filled patterned mold cavities of a mold structure includes a pattern based alignment too including means for identifying a mold training pattern image and a semiconductor training pattern image on a training mold structure and a training semiconductor structure, respectively, means for training the alignment tool with the training pattern images, means for storing the alignment tool trained position, means for identifying a mold pattern image and a semiconductor pattern image on the mold structure and the semiconductor structure matching the mold training pattern image and the semiconductor training pattern image, respectively, and means for aligning the identified mold pattern image with the semiconductor pattern image

## Claims

### Claim 1

An apparatus for forming solder bumps onto semiconductor structures comprising:
equipment for filling patterned mold cavities formed on a first surface of a mold structure with solder;
equipment for positioning and aligning a patterned first surface of a semiconductor structure directly opposite to said solder filled patterned mold cavities of the mold structure comprising:
at least one motorized alignment pin configured to be aligned with a first fiduciary marker on said mold structure and with a first fiduciary marker on said semiconductor structure; and
a pattern based alignment tool comprising means for identifying a mold training pattern image and a semiconductor training pattern image on a training mold structure and a training semiconductor structure, respectively, means for training said alignment tool with said training pattern images, means for storing said alignment tool trained position, means for identifying a mold pattern image and a semiconductor pattern image on said mold structure and said semiconductor structure matching said mold training pattern image and said semiconductor training pattern image, respectively, and means for aligning said identified mold pattern image with said identified semiconductor pattern image;
a fixture tool for holding and transferring said aligned mold and semiconductor structures together; and
solder transfer equipment for receiving said fixture tool with the aligned mold and semiconductor structures and transferring the solder from said aligned patterned mold cavities to said aligned patterned semiconductor first surface.

### Claim 2 (depends on 1)

The apparatus of claim 1 wherein said solder transfer equipment comprises:
a wafer heater stack configured to heat said semiconductor structure;
a mold heater stack configured to heat said mold structure to a process temperature slightly above said solder's melting point;
wherein said fixture tool with said aligned mold and semiconductor structures is inserted between said wafer heater stack and said mold heater stack so that a second surface opposite to said first surface of said substrate is in contact with said wafer heater stack and a second surface opposite to said first surface of said mold structure is in contact with said mold heater stack; and
wherein a deposition chamber is formed between said wafer heater stack and said mold heater stack by sealing said wafer heater stack and said mold heater stack against said frame.

### Claim 3 (depends on 1)

The apparatus of claim 1 wherein said fixture tool comprises a frame having a central aperture dimensioned to support a substrate and wherein a second surface opposite to said patterned first surface of said semiconductor structure is brought in contact with a first surface of said substrate.

### Claim 4 (depends on 3)

The apparatus of claim 3 wherein said fixture tool further comprises one or more clamp/spacer assemblies arranged symmetrically around said frame, each clamp/spacer assembly comprising a clamp configured to clamp said mold and semiconductor structures together and a spacer configured to be inserted between said first surface of said semiconductor structure and said first surface of said mold structure and thereby to separate said mold and semiconductor structures by a distance equal to said spacer's height.

### Claim 5

An apparatus for positioning and aligning a patterned surface of a first semiconductor structure directly opposite to a patterned surface of a second semiconductor structure comprising a pattern based alignment tool comprising:
means for defining first and second training pattern images on first and second training semiconductor structures, respectively;
means for training said alignment tool with said first and second training pattern images;
means for locating said first and second training pattern images;
means for storing said alignment tool trained position;
means for identifying first and second semiconductor pattern images on patterned surfaces of said first and second semiconductor structures matching said first and second training pattern images, respectively; and
means for aligning centers of said identified first and second semiconductor pattern images.

### Claim 6 (depends on 5)

The apparatus of claim 5 wherein said means for defining first and second training pattern images on first and second training semiconductor structures comprise means for defining a target area around a unique pattern of elements and means for defining an area around each element.

### Claim 7 (depends on 6)

The apparatus of claim 6 wherein said means for training said alignment tool comprises an automatic pattern recognition application.

### Claim 8 (depends on 7)

The apparatus of claim 7 wherein said automatic pattern recognition application comprises a Patmax application.

### Claim 9 (depends on 8)

The apparatus of claim 8 wherein said means for locating said training pattern image comprises means for locating said training pattern image position within a semiconductor structure search area, means for counting all elements within said training pattern image and means for locating all elements' positions within said training pattern image.

### Claim 10 (depends on 9)

The apparatus of claim 9 wherein said means for identifying said semiconductor pattern images on patterned surfaces of said semiconductor structures matching said training pattern images comprise means for matching pattern areas, number of elements within the pattern areas and positions of elements within the pattern areas.

### Claim 11 (depends on 10)

The apparatus of claim 10 further comprising means for designing a mask image based on said elements' center positions and dimensions and training said alignment tool with a pattern mask image comprising said elements masked by said mask image.

### Claim 12 (depends on 5)

The apparatus of claim 5 further comprising at least one motorized alignment pin configured to be aligned with a first fiduciary marker on said first semiconductor structure and with a first fiduciary marker on said second semiconductor structure.

### Claim 13

A method for forming solder bumps onto semiconductor structures comprising:
filling patterned mold cavities formed on a first surface of a mold structure with solder;
positioning and aligning a patterned first surface of a semiconductor structure directly opposite to said solder filled patterned mold cavities of the mold structure wherein said aligning comprises
aligning at least one motorized alignment pin with a first fiduciary marker on said mold structure and with a first fiduciary marker on said semiconductor structure; and
performing a pattern based alignment comprising identifying a mold training pattern image and a semiconductor training pattern image on a training mold structure and a training semiconductor structure, respectively, training said alignment tool with said training pattern images, storing said alignment tool trained position, identifying a mold pattern image and a semiconductor pattern image on said mold structure and said semiconductor structure matching said mold training pattern image and said semiconductor training pattern image, respectively, and aligning said identified mold pattern image with said identified semiconductor pattern image;
providing a fixture tool for holding and transferring said aligned mold and semiconductor structures together; and
inserting said fixture tool with the aligned mold and semiconductor structures into solder transfer equipment and transferring the solder from said aligned patterned mold cavities to said aligned patterned semiconductor first surface

### Claim 14 (depends on 13)

The method of claim 13 wherein said solder transfer equipment comprises:
a wafer heater stack configured to heat said semiconductor structure;
a mold heater stack configured to heat said mold structure to a process temperature slightly above said solder's melting point;
wherein said fixture tool with said aligned mold and semiconductor structures is inserted between said wafer heater stack and said mold heater stack so that a second surface opposite to said first surface of said substrate is in contact with said wafer heater stack and a second surface opposite to said first surface of said mold structure is in contact with said mold heater stack; and
wherein a deposition chamber is formed between said wafer heater stack and said mold heater stack by sealing said wafer heater stack and said mold heater stack against said frame.

### Claim 15 (depends on 13)

The method of claim 13 wherein said fixture tool comprises a frame having a central aperture dimensioned to support a substrate and wherein a second surface opposite to said patterned first surface of said semiconductor structure is brought in contact with a first surface of said substrate.

### Claim 16 (depends on 15)

The method of claim 15 wherein said fixture tool further comprises one or more clamp/spacer assemblies arranged symmetrically around said frame, each clamp/spacer assembly comprising a clamp configured to clamp said mold and semiconductor structures together and a spacer configured to be inserted between said first surface of said semiconductor structure and said first surface of said mold structure and thereby to separate said mold and semiconductor structures by a distance equal to said spacer's height.

### Claim 17

A method for positioning and aligning a patterned surface of a first semiconductor structure directly opposite to a patterned surface of a second semiconductor structure comprising performing a pattern based alignment comprising:
defining first and second training pattern images on first and second training semiconductor structures, respectively;
training said alignment tool with said first and second training pattern images;
locating said training pattern images;
storing said alignment tool trained position;
identifying first and second semiconductor pattern images on patterned surfaces of said first and second semiconductor structures matching said first and second training pattern images, respectively; and
aligning centers of said identified first and second semiconductor pattern images.

### Claim 18 (depends on 17)

The method of claim 17 wherein said defining first and second training pattern images on first and second training semiconductor structures comprise defining a target area around a unique pattern of elements and defining an area around each element.

### Claim 19 (depends on 18)

The method of claim 18 wherein said training said alignment tool comprises running an automatic pattern recognition application.

### Claim 20 (depends on 19)

The method of claim 19 wherein said automatic pattern recognition application comprises a Patmax application.

### Claim 21 (depends on 19)

The method of claim 19 wherein said locating said training pattern image comprises locating said training pattern image position within a semiconductor structure search area, counting all elements within said training pattern image and locating all elements' positions within said training pattern image.

### Claim 22 (depends on 21)

The method of claim 21 wherein said identifying said semiconductor pattern images on patterned surfaces of said semiconductor structures matching said training pattern images comprise matching pattern areas, number of elements within the pattern areas and positions of elements within the pattern areas.

### Claim 23 (depends on 22)

The method of claim 22 further comprising designing a mask image based on said elements' center positions and dimensions and training said alignment tool with a pattern mask image comprising said elements masked by said mask image.

### Claim 24 (depends on 17)

The method of claim 17 further comprising aligning at least one motorized alignment pin with a first fiduciary marker on said first semiconductor structure and with a first fiduciary marker on said second semiconductor structure.