# US 2008/0188049 A1 · Methods of Manufacturing Non-Volatile Memory Devices Including Charge-Trapping Layers

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- Number: US 2008/0188049 A1
- Document ID: US20080188049A1
- Status: Published application
- Kind: A1
- Application number: 12/022,735
- Filed: 2008-01-30
- Published: 2008-08-07
- Earliest claimed: 2007-02-01
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Woo Gwan Shim; Mong-Sup Lee; Ji-Hoon Cha; Chang-Ki Hong; Kun-Tack Lee
- Web page: https://patentgrep.com/patent/US20080188049A1

## CPC

- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 30/694: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 64/037: {comprising charge-trapping insulators}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Methods of manufacturing non-volatile memory devices are provided including sequentially forming a tunnel insulating layer, a charge-trapping layer, a blocking layer and a conductive layer on a substrate having a channel region. The conductive layer is patterned to form a word line structure, and the blocking layer and the charge-trapping layer are etched using an aqueous acid solution as an etching solution to form a blocking layer pattern and a charge-trapping layer pattern.

## Claims

### Claim 1

A method of manufacturing a non-volatile memory device, the method comprising:
forming a tunnel insulating layer, a charge-trapping layer, a blocking layer and a conductive layer on a substrate having a channel region;
patterning the conductive layer to form a word line structure;
etching the blocking layer and the charge-trapping layer using an aqueous acid solution as an etching solution to form a blocking layer pattern and a charge-trapping layer pattern over the channel region; and
forming impurity regions at surface portions of the substrate on both sides of the channel region.

### Claim 2 (depends on 1)

The method of claim 1, wherein the blocking layer comprises aluminum oxide.

### Claim 3 (depends on 1)

The method of claim 1, wherein the charge-trapping layer comprises silicon nitride.

### Claim 4 (depends on 1)

The method of claim 1, wherein the blocking layer and the charge-trapping layer are etched using an aqueous phosphoric acid solution.

### Claim 5 (depends on 4)

The method of claim 4, wherein a temperature of the aqueous phosphoric acid solution is controlled in a range of from about 100° C. to about 200° C.

### Claim 6 (depends on 4)

The method of claim 4, wherein the aqueous phosphoric acid solution comprises from about 5.0 to about 50 percent by weight of water.

### Claim 7 (depends on 4)

The method of claim 4, wherein etching the blocking layer and the charge-trapping layer comprises:
placing the substrate in a container receiving the aqueous phosphoric acid solution to immerse the substrate in the aqueous phosphoric acid solution;
closing the container such that the container is air tight; and
heating the airtight container to raise a temperature of the aqueous phosphoric acid solution.

### Claim 8 (depends on 7)

The method of claim 7, wherein forming the blocking layer pattern and the charge-trapping layer pattern is followed by cooling the container to lower the temperature of the aqueous phosphoric acid solution.

### Claim 9 (depends on 7)

The method of claim 7, wherein an inert gas is supplied into the container.

### Claim 10 (depends on 1)

The method of claim 1, wherein etching the blocking layer and the charge-trapping layer comprises:
etching the blocking layer using an aqueous phosphoric acid solution to form the blocking layer pattern; and
etching the charge-trapping layer pattern using an aqueous sulfuric acid solution to form the charge-trapping layer pattern.

### Claim 11 (depends on 10)

The method of claim 10, wherein a temperature of the aqueous phosphoric acid solution is controlled in a range of from about 100° C. to about 200° C.

### Claim 12 (depends on 10)

The method of claim 10, wherein the aqueous phosphoric acid solution comprises from about 5.0 to about 50 percent by weight of water.

### Claim 13 (depends on 10)

The method of claim 10, wherein etching the blocking layer comprises:
placing the substrate in a container receiving the aqueous phosphoric acid solution to immerse the substrate in the aqueous phosphoric acid solution;
closing the container such that the container is airtight; and
heating the airtight container to raise a temperature of the aqueous phosphoric acid solution.

### Claim 14 (depends on 13)

The method of claim 13, further comprising cooling the container to lower the temperature of the aqueous phosphoric acid solution after forming the blocking layer pattern.

### Claim 15 (depends on 13)

The method of claim 13, wherein an inert gas is supplied into the container.

### Claim 16 (depends on 10)

The method of claim 10, wherein a temperature of the aqueous sulfuric acid solution is controlled in a range of from about 100° C. to about 200° C.

### Claim 17 (depends on 10)

The method of claim 10, wherein the aqueous sulfuric acid solution comprises from about 5.0 to about 50 percent by weight of water.

### Claim 18 (depends on 10)

The method of claim 10, wherein etching the charge-trapping layer comprises:
placing the substrate in a container receiving the aqueous sulfuric acid solution to immerse the substrate in the aqueous sulfuric acid solution;
closing the container such that the container is airtight; and
heating the airtight container to raise a temperature of the aqueous sulfuric acid solution.

### Claim 19 (depends on 18)

The method of claim 18, further comprising cooling the container to lower the temperature of the aqueous sulfuric acid solution after forming the charge-trapping layer pattern.

### Claim 20 (depends on 18)

The method of claim 18, wherein an inert gas is supplied into the container.

### Claim 21 (depends on 1)

The method of claim 1, wherein the charge-trapping layer pattern is formed using an aqueous oxalic acid solution.

### Claim 22 (depends on 1)

The method of claim 1, further comprising forming spacers on side surfaces of the word line structure.

### Claim 23 (depends on 22)

The method of claim 22, wherein each of the spacers comprises silicon oxide and silicon nitride.

### Claim 24 (depends on 23)

The method of claim 23, wherein forming the spacers comprises:
forming a silicon oxide layer on the word line structure and the blocking layer;
forming a silicon nitride layer on the silicon oxide layer; and
anisotropically etching the silicon nitride layer and the silicon oxide layer to form the spacers.