# US 2008/0188048 A1 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2008/0188048 A1 - Document ID: US20080188048A1 - Status: Published application - Kind: A1 - Application number: 12/073,488 - Filed: 2008-03-06 - Published: 2008-08-07 - Earliest claimed: 2004-09-28 - Assignees: NEC Electronics Corporation - Inventors: Takayuki Nagai - Web page: https://patentgrep.com/patent/US20080188048A1 ## CPC - H10D 30/0212: {using self-aligned silicidation} - H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET} - H10D 30/023: {having multiple independently-addressable gate electrodes influencing the same channel (manufacture or treatment of dual gate TFTs H10D30/031)} - H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)} - H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]} - H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)} - H10D 64/111: {Field plates} - H10D 64/519: {characterised by their top-view geometrical layouts} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract The invention provides a semiconductor apparatus capable of achieving a device having a snap-back resisting pressure of about 5 to 10 V by a self-aligning process. The semiconductor apparatus includes two or more sub-gates placed next to a main gate at a predetermined interval, and low concentration layers placed continuously from the ends of source/drain layers to near the end of the main gate, having a potential type same as that of the source/drain layers, and having an impurity concentration lower than that of the source/drain layers. ## Claims ### Claim 1 A method of forming a MOS transistor, comprising: forming a conductive film over a semiconductor substrate; selectively removing said film to leave a continuous pattern of said film having a main gate portion, a sub-gate portion and a connection portion, said main gate portion and said sub-gate portion being adjacent to each other with a space therebetween where said film was removed; forming a source/drain region on said substrate; and forming an impurity diffusion region placed continuously from the end of said source/drain region to near the end of said main gate under said sub-gate, said impurity region having a conductivity type which is the same as that of said source/drain region and having an impurity concentration lower than that of said source/drain region. ### Claim 2 (depends on 1) The method as claimed in claim 1, wherein the source/drain region is formed using the conductive film as a mask. ### Claim 3 (depends on 1) The method as claimed in claim 1, wherein the sub-gate portion comprises sub-gates formed next to said main gate on both sides of said main gate. ### Claim 4 (depends on 3) The method as claimed in claim 3, wherein a number of said sub-gates next to said main gate on one side is different from the number of said sub-gates formed on the other side. ### Claim 5 (depends on 1) The method as claimed in claim 1, wherein said sub-gate is placed next to said main gate only on the drain side. ### Claim 6 (depends on 5) The method as claimed in claim 5, wherein said impurity diffusion region is formed only on the drain side. ### Claim 7 (depends on 1) The method as claimed in claim 1, wherein said impurity diffusion region is a lightly doped drain (LDD) region. ### Claim 8 (depends on 1) The method as claimed in claim 1, wherein said impurity diffusion region is a double diffused drain (DDD) layer. ### Claim 9 (depends on 1) The method as claimed in claim 1, wherein said impurity diffusion is an extension region. ### Claim 10 (depends on 1) The method as claimed in claim 1, further comprising a side wall formed between said main gate and said sub-gate not to link said main gate with said sub-gate. ### Claim 11 (depends on 1) The method as claimed in claim 1, further comprising a side wall formed between said main gate and said sub-gate to link said main gate with said sub-gate. ### Claim 12 (depends on 1) The method as claimed in claim 1, further comprising a second source/drain region formed in said impurity diffusion region and between said main gate and said sub-gate. ### Claim 13 (depends on 12) The method as claimed in claim 12, further comprising a silicide layer placed on the surface of said second source/drain region. ### Claim 14 (depends on 1) The method as claimed in claim 1, wherein said transistor is an NMOS type transistor or PMOS type transistor. ### Claim 15 (depends on 14) The method as claimed in claim 14, wherein said transistor is formed on a semiconductor device having transistors having mutually different breakdown resisting pressures. ### Claim 16 (depends on 15) The method as claimed in claim 15, wherein said substrate is a P type silicon substrate or N type silicon substrate. ### Claim 17 (depends on 1) The method as claimed in claim 1, wherein the impurity diffusion region is formed using the conductive film as a mask. ### Claim 18 A method of forming a MOS transistor, comprising: forming a semiconductor substrate of a first conductivity type; forming an element isolation region on said semiconductor substrate to define an element formation region; forming a main gate and at least one sub-gate on said element formation region, said at least one sub-gate being adjacent to said main gate, said at least one sub-gate and said main gate being formed from a single unitary conductive element so that the main gate and the at least one sub-gate are in direct contact at a first portion and are separated at a second portion in a same plane; forming at least one source/drain region of a second conductivity type between said sub gate and said element isolation region, said second conductivity type being different from said first conductivity type; and forming at least one impurity diffusion region of said second conductivity type between said source/drain region and said main gate under said sub-gate, said impurity diffusion region having an impurity concentration lower than that of said source/drain region.