# US 2008/0188044 A1 · Semiconductor devices with dual-metal gate structures and fabrication methods thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2008/0188044 A1 - Document ID: US20080188044A1 - Status: Published application - Kind: A1 - Application number: 12/099,827 - Filed: 2008-04-09 - Published: 2008-08-07 - Earliest claimed: 2006-10-25 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Peng-Fu Hsu; Fong-Yu Yen; Yi-Shien Mor; Huan-Just Lin; Ying Jin; Hun-Jan Tao - Web page: https://patentgrep.com/patent/US20080188044A1 ## CPC - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)} - H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)} - H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)} - H10D 84/0177: {the gate conductors having different materials or different implants} - H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS} - H10D 64/685: {being perpendicular to the channel plane} - H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)} - H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Semiconductor devices with dual-metal gate structures and fabrication methods thereof. A semiconductor substrate with a first doped region and a second doped region separated by an insulation layer is provided. A first metal gate stack is formed on the first doped region, and a second metal gate stack is formed on the second doped region. A sealing layer is disposed on sidewalls of the first gate stack and the second gate stack. The first metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a first metal layer on the high-k dielectric layer, a metal insertion layer on the first metal layer, a second metal layer on the metal insertion layer, and a polysilicon layer on the second metal layer. The second metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a second metal layer on the high-k dielectric layer, and a polysilicon layer on the second metal layer. ## Claims ### Claim 1 A method for fabricating a CMOS device with dual-metal gate structures, comprising: providing a semiconductor substrate with a first doped region and a second doped region separated by an insulation layer; forming an interfacial layer on the semiconductor substrate; forming a high-k dielectric layer on the interfacial layer; forming a first metal layer on the high-k dielectric layer; forming a metal insertion layer on the first metal layer; patterning the metal insertion layer, the first metal layer, the high-k dielectric layer, and the interfacial layer exposing the second doped region of the semiconductor substrate; conformably forming a second metal layer on the metal insertion layer and the second doped region of the semiconductor substrate; forming a polysilicon layer on the second metal layer; patterning a first metal gate stack and a second metal gate stack on the first and the second doped regions of the semiconductor substrate; forming a sealing layer on sidewalls of the first gate stack and the second gate stack. ### Claim 2 (depends on 1) The method according to claim 1, wherein the interfacial layer is formed resulting from wafer cleaning processes, or wherein the interfacial layer is formed by thermal or chemical oxidation. ### Claim 3 (depends on 1) The method according to claim 1, wherein the high-k dielectric layer is formed by atomic layered deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). ### Claim 4 (depends on 3) The method according to claim 3, wherein a silicon atomic ratio and a dielectric constant of the high-k dielectric layer are adjusted during ALD, CVD, and PVD. ### Claim 5 (depends on 3) The method according to claim 3, wherein adjusting an Hf and a Si precursor cycle numbers during a nano-laminated ALD forms the high-k dielectric layer comprising a HfSiOx with 30-80% silicon atomic ratio and 7-20 dielectric constant. ### Claim 6 (depends on 1) The method according to claim 1, further comprising a nitrification process during or after the formation of the high-k dielectric layer. ### Claim 7 (depends on 6) The method according to claim 6, wherein the high-k dielectric layer is nitrified by thermal or plasma nitrification. ### Claim 8 (depends on 1) The method according to claim 1, wherein the first metal layer and the second metal layer are separately formed by ALD or PVD. ### Claim 9 (depends on 1) The method according to claim 1, wherein the second metal layer is formed after removal of the first metal layer from the second doped region. ### Claim 10 (depends on 1) The method according to claim 1, wherein the first metal gate stack comprises a tri-layer metal structure comprising the first metal layer, the metal insertion layer, and the second metal layer, and wherein the second metal gate stack comprises a mono-layer metal structure comprising the second metal layer. ### Claim 11 (depends on 1) The method according to claim 1, wherein the metal insertion layer is directly formed by ALD or PVD after formation of the first metal layer. ### Claim 12 (depends on 1) The method according to claim 1, wherein the first metal layer and the metal insertion layer are separately formed in different chambers sharing the same transfer chamber without breaking the vacuum. ### Claim 13 (depends on 1) The method according to claim 1, wherein the step of patterning a first metal gate stack and a second metal gate stack comprises removal of the first metal layer and the second metal layer by dry etching, wet etching, or combination thereof. ### Claim 14 (depends on 13) The method according to claim 13, wherein the insertion metal layer serves as protection of the first metal layer from patterning the first metal gate stack and the second metal gate stack. ### Claim 15 (depends on 1) The method according to claim 1, wherein the polysilicon layer is formed by chemical vapor deposition. ### Claim 16 (depends on 1) The method according to claim 1, wherein the sealing layer is formed by CVD or ALD. ### Claim 17 (depends on 1) The method according to claim 1, wherein the sealing layer is etched by an anisotropic etching process remaining on sidewalls of the first gate stack and the second gate stack.