# US 2008/0188041 A1 · Lateral undercut of metal gate in SOI device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2008/0188041 A1
- Document ID: US20080188041A1
- Status: Published application
- Kind: A1
- Application number: 12/079,587
- Filed: 2008-03-26
- Published: 2008-08-07
- Earliest claimed: 2005-08-17
- Assignees: Intel Corporation
- Inventors: Suman Datta; Justin K. Brask; Jack Kavalieros; Brian S. Doyle; Gilbert Dewey; Mark L. Doczy; Robert S. Chau
- Web page: https://patentgrep.com/patent/US20080188041A1

## CPC

- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6744: {Monocrystalline silicon}
- H10D 64/01324: {characterised by the sectional shape, e.g. T or inverted-T}
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer, source/drain extensions a distance beneath the metal gate, and lateral undercuts in the sides of the metal gate.

## Claims

### Claim 1

A method for making a semiconductor device, comprising:
forming a gate dielectric on a second semiconductor layer on an insulator layer that is on a first semiconductor layer;
forming a metal gate electrode on the gate dielectric, the metal gate electrode having a first side and a second side;
removing portions of the metal gate electrode on the first side and the second side to form lateral undercuts with a depth;
forming source/drain regions of the second semiconductor layer on the first and second side of the metal gate electrode, the source/drain regions having extensions a distance beneath the metal gate electrode; and
wherein the depth of the lateral undercuts are at least about one-fourth the distance of the source/drain region extensions.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming a layer of dielectric material on the second semiconductor layer;
forming a metal layer on the layer of dielectric material;
removing portions of the metal layer to leave behind the metal gate electrode; and
removing portions of the layer of dielectric material to leave behind the gate dielectric.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
determining a desired threshold voltage for the semiconductor device;
determining a thickness of the metal gate electrode that results in the desired threshold voltage; and
wherein forming a metal layer on the layer of dielectric material comprises forming the metal layer with a thickness about equal to the thickness of the metal gate electrode that results in the desired threshold voltage.

### Claim 4 (depends on 2)

The method of claim 2, wherein the layer of dielectric material comprises a high-k dielectric material and wherein the metal layer on the layer of dielectric material comprises a material selected from the group consisting of a p-type metal, an n-type metal, and a mid-gap metal.