# US 2008/0188039 A1 · Method of fabricating chip package structure

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- Number: US 2008/0188039 A1
- Document ID: US20080188039A1
- Status: Published application
- Kind: A1
- Application number: 11/949,776
- Filed: 2007-12-04
- Published: 2008-08-07
- Earliest claimed: 2007-02-06
- Assignees: ChipMOS Technologies (Bermuda) Ltd.
- Inventors: Jie-Hung Chiou; Yong-Chao Qiao; Yan-Yi Wu
- Web page: https://patentgrep.com/patent/US20080188039A1

## CPC

- H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)}
- H10W 70/042: {Etching}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 72/073: {of die-attach connectors}
- H10W 72/075: {of bond wires}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/10: characterised by their shape or disposition
- H10W 74/127: {characterised by arrangements for sealing or adhesion}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of fabricating a chip package structure includes the steps of providing a lead frame having a die pad, plural leads and at least one structure enhancement element. A chip is then disposed on the die pad and plural bonding wires are formed to electrically connect the chip to the leads. Then, an upper encapsulant and a first lower encapsulant are formed on an upper surface and a lower surface of the lead frame, respectively. The first lower encapsulant has plural concaves to expose the structure enhancement element. Finally, the structure enhancement element is etched with use of the first lower encapsulant as an etching mask until the die pad and one of the leads connected by the structure enhancement element, or two of the adjacent leads connected thereby are electrically insulated.

## Claims

### Claim 1

A method of fabricating a chip package structure, comprising:
providing a lead frame having an upper surface and a lower surface, wherein the lead frame comprises a die pad, a plurality of leads surrounding the die pad, and at least a structure enhancement element connecting the die pad to one of the leads, or connecting two of the adjacent leads;
providing a chip having an active surface, a back surface, and a plurality of chip bonding pads disposed on the active surface;
adhering the back surface of the chip to the die pad;
forming a plurality of bonding wires so as to electrically connect the chip bonding pads and the leads, respectively;
forming an upper encapsulant and a lower encapsulant, wherein the upper encapsulant encapsulates the upper surface of the lead frame, the chip and the bonding wires, while the lower encapsulant encapsulates the lower surface of the lead frame and has at least a concave so as to expose the structure enhancement element; and
etching the structure enhancement element with use of the lower encapsulant as an etching mask until the die pad and one of the leads connected by the structure enhancement element or two of the adjacent leads connected thereby are electrically insulated.

### Claim 2 (depends on 1)

The method of fabricating the chip package structure of claim 1, wherein the bonding wires are formed through a wire bonding technique.

### Claim 3 (depends on 1)

The method of fabricating the chip package structure of claim 1, further comprising filling an encapsulant into the concave of the lower encapsulant.

### Claim 4

A method of fabricating a chip package structure, comprising:
providing a lead frame having an upper surface and a lower surface, wherein the lead frame comprises a die pad, a plurality of leads surrounding the die pad, and at least a structure enhancement element connecting the die pad to one of the leads, or connecting two of the adjacent leads;
providing a chip having an active surface, a back surface, and a plurality of chip bonding pads disposed on the active surface;
adhering the back surface of the chip to the die pad;
forming a plurality of bonding wires so as to electrically connect the chip bonding pads and the leads, respectively;
forming an upper encapsulant encapsulating the upper surface of the lead frame, the chip, and the bonding wires;
forming an etching mask on the lower surface of the lead frame so as to expose the structure enhancement element; and
etching the lead frame exposed by the etching mask until the die pad and one of the leads connected by the structure enhancement element or two of the adjacent leads connected thereby are electrically insulated.

### Claim 5 (depends on 4)

The method of fabricating the chip package structure of claim 4, further comprising forming a lower encapsulant filled between the die pad and the leads after the lead frame exposed by the etching mask is etched.

### Claim 6 (depends on 5)

The method of fabricating the chip package structure of claim 5, wherein the lower encapsulant is coplanar with the etching mask.

### Claim 7 (depends on 5)

The method of fabricating the chip package structure of claim 5, wherein the lower encapsulant further encapsulates the etching mask.

### Claim 8 (depends on 5)

The method of fabricating the chip package structure of claim 5, further comprising removing the etching mask and then forming the lower encapsulant after the step of etching the metal thin plate is performed.

### Claim 9 (depends on 4)

The method of fabricating the chip package structure of claim 4, wherein the bonding wires are formed through a wire bonding technique.

### Claim 10 (depends on 4)

The method of fabricating the chip package structure of claim 4, wherein the etching mask is a patterned photoresist layer or a patterned solder mask layer.