# US 2008/0187079 A1 · Data recovery circuits using oversampling for best data sample selection

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- Number: US 2008/0187079 A1
- Document ID: US20080187079A1
- Status: Published application
- Kind: A1
- Application number: 12/061,956
- Filed: 2008-04-03
- Published: 2008-08-07
- Earliest claimed: 2003-12-19
- Assignees: International Business Machines Corporation
- Inventors: Vincent Vallet
- Web page: https://patentgrep.com/patent/US20080187079A1

## CPC

- H04L 25/03828: {Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties (partial response systems H04L25/497)}
- H04L 7/0338: {the correction of the phase error being performed by a feed forward loop}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

An improved data recovery circuit based on an oversampling technique to select the best data sample to be kept as the data to recover that is only based on accumulating the data edges (or transitions). The incoming serial data stream with jitter is oversampled in an oversampling circuit by means of the multiple phases of a reference clock (clk) to produce data samples. Each sample is compared to the sample(s) collected with the next clock phase(s) in an edge detector circuit to determine the presence of a data edge and the edge information is stored and accumulated in a data edge memory. A selection determination circuit uses the memorized edge information to indicate which sample is the farthest from the data edges. A selection validation circuit validates the selection to avoid false determination due to jitter and skew.

## Claims

### Claim at position 1

1-4. (canceled)

### Claim 5

A method for recovering the data in an incoming data stream with jitter and skewed with respect to a reference clock by selecting the best data sample in a set of data samples obtained by oversampling said incoming data stream comprising the steps of:
oversampling the incoming data stream with the n phases of the reference clock to generate a set of n data samples;
detecting the position of the data edges (or transitions) in the set of data samples and creating a map of n bits, representing the data edge information, i.e. the edge positions, by assigning a determined binary logic value to said data edge positions and the opposite value otherwise;
memorizing the map of n bits wherein the bits are at a first binary logic level for detected data edges and at a second binary logic level otherwise and wherein the last bit map position is considered as adjacent to the first bit map position (and conversely);
determining which data sample is the farthest from the data edges, i.e. which data sample is the best candidate for the data to recover;
validating said selection signals to generate validated selection signals to avoid false determination due to jitter and skew;
memorizing said validated selection signals; and,
using said memorized validated selection signals and said data samples to select the best data sample to represent the recovered data.

### Claim 6 (depends on 5)

The method of claim 5 wherein the bit map is memorized during several reference clock periods.

### Claim 7 (depends on 5)

The method of claim 5 wherein said determination consists to compare two consecutive data samples and to generate a corresponding set of signals representing the data edge information, i.e. the data edge positions, so that when a transition is detected between two consecutive data samples the signal is a first logic level (e.g. ‘1’) and at a second logic level (i.e. ‘0’) otherwise.

### Claim 8 (depends on 5)

The method of claim 5 wherein said oversampling is performed by using the multiple phases of a reference clock.