# US 2008/0186998 A1 · Network-On-Chip Environment and Method for Reduction of Latency

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- Number: US 2008/0186998 A1
- Document ID: US20080186998A1
- Status: Published application
- Kind: A1
- Application number: 11/910,749
- Filed: 2006-04-04
- Published: 2008-08-07
- Earliest claimed: 2005-04-06
- Assignees: Koninklijke Philips Electronics N.V.
- Inventors: Edwin Rijpkema
- Web page: https://patentgrep.com/patent/US20080186998A1

## CPC

- H04L 47/10: Flow control; Congestion control
- H04L 45/40: {Wormhole routing}
- H04L 47/245: {using preemption}
- H04L 47/283: in response to processing delays, e.g. caused by jitter or round trip time [RTT]
- H04L 47/39: {Credit based}
- H04J 2203/0091: Time slot assignment
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S)

## Abstract

The invention relates to an integrated circuit comprising a plurality of processing modules (IP) and a network (NoC) arranged for coupling processing modules (IP), comprising: the processing module (IP) includes an associated network interface (NI) which is provided for transmitting data to the network (NoC) supplied by the associated processing module and for receiving data from the network (NoC) destined for the associated processing module, wherein the data transmission between processing modules (IP) operates based on time division multiple access (TDMA) using time slots (S) and contention free transmission by using channels (a-d); each network interface (NI) includes a slot table (ST) for storing an allocation of a time slot to a certain channel (a-d), wherein at least a part of the time slots (0-9) allocated to channels (a-d) originated from the same network interface (NI) are shared for transmission of data of the set of channels (a-d). The invention uses the idea to utilize all or at least a part of slots of channels (a-d) in common, which are originating from the same network interface (NI). This will at first reduce the latency of such channels (a-d). Additionally the sizes of the slot tables (ST) in all network components (NI, R1 1-R44) are reduced drastically.

## Claims

### Claim 1

Integrated circuit comprising a plurality of processing modules (IP) and a network (NoC) arranged for coupling processing modules (IP),
wherein each processing module (IP) includes an associated network interface (NI) which is provided for transmitting data to the network (NoC) and for receiving data from the network (NoC);
wherein data transmission between processing modules (IP) operates based on time division multiple access (TDMA) using time slots (S) and contention free transmission by using channels (a-d); and
wherein each network interface (NI) includes a slot table (ST) for storing an allocation of a time slot to a certain channel (a-d), wherein at least a part of the time slots (0-9) allocated to channels (a-d) originated from the same network interface (NI) are shared for transmission of data of the set of channels (a-d).

### Claim 2 (depends on 1)

Integrated circuit as claimed in claim 1, wherein all slots (0-9) allocated to the channels (a-d) are shared and are used in common for data transmission of the set of channels (a-d) from the same network interface (NI).

### Claim 3 (depends on 1)

Integrated circuit as claimed in claim 1, including a scheduler (55) included in the network interface (NI), the scheduler (55) is provided for scheduling the data of the set of channels to the shared slots (S).

### Claim 4 (depends on 1)

Integrated circuit as claimed in claim 1, wherein data of a channels (a-d) are scheduled by the scheduler (55) depending on the position in a queue (44).

### Claim 5 (depends on 1)

Integrated circuit as claimed in claim 1, wherein a scheduling of data of the set of channel is performed depending the filling status of the queue (44) of the set of the channels.

### Claim 6 (depends on 1)

Integrated circuit as claimed in claim 1, wherein the data of channels allocated to the set of channels is queued in a single queue (44).

### Claim 7

Method for allocating time slots for data transmission in an integrated circuit, the integrated circuit having a plurality of processing modules (IP) with a network interface (NI) and a network (NoC), the method comprising the steps of:
communicating between processing modules (IP) based on time division multiple access (TDMA) using time slots and contention free transmission by using channels (a-d);
storing a slot table (ST) in each network interface (NI) including an allocation of a time slot to a certain channel (a-d), and
sharing of time slots (S) allocated to channels originating from the same network interface (NI).

### Claim 8

Data processing system comprising:
a plurality of processing modules (IP) and a network (NoC) arranged for coupling the processing modules (IP); and
a network interface (NI) associated to each processing module (IP) which is provided for transmitting data to the network (NoC) and for receiving data from the network (NoC);
wherein data transmission between processing modules (IP) operates based on time division multiple access (TDMA) using time slots and contention free transmission by using a channels (a-d);
each network interface (NI) includes a slot table (ST) for storing an allocation of a time slot to a certain channel (a-d); and
a sharing is provided of time slots (S) allocated to channels (a-d) originating from the same network interface (NI).