# US 2008/0186797 A1 · Circuit for use in a multiple block memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2008/0186797 A1 - Document ID: US20080186797A1 - Status: Published application - Kind: A1 - Application number: 11/672,279 - Filed: 2007-02-07 - Published: 2008-08-07 - Earliest claimed: 2007-02-07 - Assignees: Freescale Semiconductor, Inc. - Inventors: Hamed Ghassemi; Huy B. Nguyen - Web page: https://patentgrep.com/patent/US20080186797A1 ## CPC - G11C 7/1051: {Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits} - G06F 12/0893: Caches characterised by their organisation or structure - G11C 7/106: {Data output latches} - G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection - G11C 2207/2245: Memory devices with an internal cache buffer - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A portion of a memory may include a first memory block, comprising a first memory cell coupled to a first memory data line, a second memory block, comprising a second memory cell coupled to a second memory data line, and a latch, having a first terminal and a second terminal. The portion of the memory may further include a first N-channel transistor, having a first current electrode coupled to the first terminal of the latch, having a second current electrode coupled to a first power supply voltage, and having a control electrode coupled to the first memory data line. The portion of the memory may further include a second N-channel transistor, having a first current electrode coupled to the first terminal of the latch, having a second current electrode coupled to the first power supply voltage, and having a control electrode coupled to the second memory data line. ## Claims ### Claim 1 A circuit portion, comprising: a latch, having a first terminal and having a second terminal; a first N-channel transistor, having a first current electrode, a second current electrode coupled to a power supply voltage, and a control electrode coupled to a first conductor of a first differential pair; a second N-channel transistor, having a first current electrode coupled to the first current electrode of the first N-channel transistor and coupled to the first terminal of the latch, a second current electrode coupled to the power supply voltage, and a control electrode coupled to a first conductor of a second differential pair; a third N-channel transistor, having a first current electrode, a second current electrode coupled to the power supply voltage, and a control electrode coupled to a second conductor of the first differential pair; and a fourth N-channel transistor, having a first current electrode coupled to the first current electrode of the third N-channel transistor and coupled to the second terminal of the latch, a second current electrode coupled to the power supply voltage, and a control electrode coupled to a second conductor of the second differential pair. ### Claim 2 (depends on 1) A circuit portion as in claim 1, wherein only one of the first transistor, the second transistor, the third transistor, and the fourth transistor is conducting at any time. ### Claim 3 (depends on 1) A circuit portion as in claim 1, wherein the latch comprises cross-coupled inverters. ### Claim 4 (depends on 1) A circuit portion as in claim 1, further comprising: a first sense amplifier for providing the first differential pair; and a second sense amplifier for providing the second differential pair. ### Claim 5 (depends on 1) A circuit portion as in claim 1, wherein the circuit portion is formed as part of a static random access memory or a cache. ### Claim 6 (depends on 5) A circuit portion as in claim 5, wherein the cache comprises a level two cache. ### Claim 7 (depends on 5) A circuit portion as in claim 5, wherein the first differential pair is associated with a first cache way and the second differential pair is associated with a second cache way. ### Claim 8 (depends on 7) A circuit portion as in claim 7, wherein the first cache way and the second cache way are not selected at a same time. ### Claim 9 (depends on 1) A circuit portion as in claim 1, wherein the power supply voltage is approximately ground. ### Claim 10 A memory, comprising: a first memory block, comprising a first memory cell coupled to a first memory data line; a second memory block, comprising a second memory cell coupled to a second memory data line; a latch, having a first terminal and a second terminal; a first N-channel transistor, having a first current electrode coupled to the first terminal of the latch, having a second current electrode coupled to a power supply voltage, and having a control electrode coupled to the first memory data line; and a second N-channel transistor, having a first current electrode coupled to the first terminal of the latch, having a second current electrode coupled to the power supply voltage, and having a control electrode coupled to the second memory data line. ### Claim 11 (depends on 10) A memory as in claim 10, wherein the first memory block further comprises a third memory data line and wherein the second memory block further comprises a fourth memory data line, and wherein the first memory data line and the third memory data line comprise a first differential pair, and wherein the second memory data line and the fourth memory data line comprise a second differential pair, the memory further comprising: a third N-channel transistor, having a first current electrode coupled to the second terminal of the latch, having a second current electrode coupled to the power supply voltage, and having a control electrode coupled to the third memory data line; and a fourth N-channel transistor, having a first current electrode coupled to the second terminal of the latch, having a second current electrode coupled to the power supply voltage, and having a control electrode coupled to the fourth memory data line. ### Claim 12 (depends on 11) A memory as in claim 11, wherein only one of the first transistor, the second transistor, the third transistor, and the fourth transistor is conducting at any time. ### Claim 13 (depends on 10) A memory as in claim 10, wherein the latch comprises cross-coupled inverters. ### Claim 14 (depends on 11) A memory as in claim 11, further comprising: a first sense amplifier for providing the first differential pair; and a second sense amplifier for providing the second differential pair. ### Claim 15 (depends on 10) A memory as in claim 10, wherein the memory comprises a static random access memory. ### Claim 16 (depends on 11) A memory as in claim 11, wherein the memory is formed as part of a cache. ### Claim 17 (depends on 16) A memory as in claim 16, wherein the cache comprises a level two cache. ### Claim 18 (depends on 16) A circuit portion as in claim 16, wherein the first differential pair is associated with a first cache way and the second differential pair is associated with a second cache way. ### Claim 19 A method for multiplexing in a memory, the method comprising: providing a first memory block; providing a second memory block; providing a first pair of differential data outputs from the first memory block; providing a second pair of differential data outputs from the second memory block; and multiplexing the first pair of differential data outputs and the second pair of differential data outputs using a plurality of common-drain connected N-channel transistors to provide an output. ### Claim 20 (depends on 19) A method as in claim 19, wherein no more than one of the plurality of common-drain connected N-channel transistors is conducting at any time.