# US 2008/0186791 A1 · Elastic Power for Read and Write Margins

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- Number: US 2008/0186791 A1
- Document ID: US20080186791A1
- Status: Published application
- Kind: A1
- Application number: 11/932,967
- Filed: 2007-10-31
- Published: 2008-08-07
- Earliest claimed: 2007-02-02
- Assignees: Montalvo Systems, Inc.
- Inventors: Yolin Lih; Ajay Bhatia; Dennis Wendell; Jun Liu; Daniel Fung; Shyam Balasubramanian
- Web page: https://patentgrep.com/patent/US20080186791A1

## CPC

- G11C 11/419: Read-write [R-W] circuits
- G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)}
- G11C 11/417: for memory cells of the field-effect type
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An elastic power header device and methods of operation are provided to improve both the read and the write margin of static random access memory (SRAM) cells by increasing read stability, reducing read disturbance and improving the Signal to Noise Margin (SNM) figure of merit. For example, various implementations of an elastic power header device are utilized as programmable resistances to permit the power supply lines to reach a maximum voltage. Allowing the power supply lines to reach the reference voltage allows more flexibility in read margin, write margin and read stability. Furthermore, this additional flexibility can be controlled by means for adjusting a voltage. This adjustment voltage can fine-tune the programmable resistances so that the read margin and the write margin can be more conveniently controlled.

## Claims

### Claim at position 1

1-24. (canceled)

### Claim 25

A memory device comprising:
a first power supply line;
a second power supply line;
a static random access memory (SRAM) cell comprising a first logic gate and a second logic gate that are cross-coupled, wherein the first power supply line supplies the first logic gate, and the second power supply line supplies the second logic gate; and
an elastic power header device connected between a reference voltage and each one of the first power supply line and the second power supply line wherein the elastic power header device is configured to provide, during a write operation of the first SRAM cell, different power supply levels on the first power supply line and the second power supply line and is configured to provide, during a read operation, a first resistance in the first power supply line and a second resistance in the second power supply line.

### Claim 26 (depends on 25)

The memory device of claim 25, wherein at least one of the first and second resistances comprise a programmable resistance.

### Claim 27 (depends on 25)

The memory device of claim 25 wherein, during the write operation, the first power supply line has a different voltage level than the second power supply line.

### Claim 28 (depends on 25)

The memory device of claim 25 wherein, during the write operation, the first power supply line has a different current flow than the second power supply line.

### Claim 29 (depends on 25)

The memory device of claim 25 wherein, during the write operation, the difference of the power supply levels is held at an adjustable strength according to a control signal.

### Claim 30 (depends on 25)

The memory device of claim 25 wherein, during the write operation, which of the first and the second power supply lines has a higher power supply level is determined by the value of the data bit being written.

### Claim 31 (depends on 25)

The memory device of claim 25 wherein, during the read operation, the first resistance and the second resistance are substantially equal, whereby a difference in power supply levels between the first power supply line and the second power supply line depends on the current drawn from each power supply line.

### Claim 32 (depends on 25)

The memory device of claim 25 wherein, during the write operation, the different power supply levels are provided by a variable resistance in a selected one of the power supply lines to facilitate writing into the first SRAM cell.

### Claim 33 (depends on 25)

The memory device of claim 25, further comprising a transistor connected between the reference voltage and a selected one of the power supply lines, wherein the transistor is configured to provide the first resistance.

### Claim 34 (depends on 25)

The memory device of claim 25, further comprising a transistor connected between the reference voltage and a selected one of the power supply lines, wherein the transistor is configured to provide the second resistance.

### Claim 35 (depends on 25)

The memory device of claim 25, wherein the different power supply levels between the first power supply line and the second power supply line during the write operation corresponds to a threshold voltage drop across a transistor.

### Claim 36 (depends on 25)

The memory device of claim 25, further comprising a keeper circuit for limiting the difference between the first power supply line and the second power supply line.

### Claim 37 (depends on 25)

The memory device of claim 25, wherein the memory device is configured for use in at least one of: an embedded SRAM memory device, a standalone SRAM memory device, a cache, a register file, a multi-port memory, a translation lookaside buffer, a content-addressable memory, or a ternary content-addressable memory.

### Claim 38

A method for achieving improved read and write margins in a memory device comprising a first power supply line, a second power supply line, and a first logic gate and a second logic gate that are cross-coupled, the method comprising:
maintaining, during a read operation of the memory device, a resistance in each one of the first power supply line and the second power supply line to provide a power supply level greater than a predetermined value; and
varying, during a write operation of the memory device, a resistance in a selected one of the first power supply line and the second power supply line to provide a power supply level difference between the first power supply line and the second power supply line.

### Claim 39 (depends on 38)

The method of claim 38, wherein the resistance comprises a programmable resistance.

### Claim 40 (depends on 38)

The method of claim 38, wherein the power supply level comprises a voltage.

### Claim 41 (depends on 38)

The method of claim 38, wherein the power supply level comprises a current.

### Claim 42 (depends on 38)

The method of claim 38, further comprising controlling a device configured to achieve a resistance.

### Claim 43 (depends on 38)

The method of claim 38, further comprising varying a conductance of a transistor connected between a reference voltage and the selected one of the first power supply line and the second power supply line.

### Claim 44 (depends on 38)

The method of claim 38, further comprising equalizing the first power supply line and the second power supply line at a time when neither of the read or the write operations is occurring.

### Claim 45

An elastic power header device for providing a first power supply line and a second power supply line in a split power fashion to a memory device, comprising:
a first conductive path, coupled between a reference voltage and both the first power supply line and the second power supply line, configured to provide a first power supply level difference between the reference voltage and each one of the first power supply line and the second power supply line;
a second conductive path, coupled between the reference voltage and the first power supply line;
a third conductive path, coupled between the reference voltage and the second power supply line, wherein, in response to a read operation, a resistance in a selected one of the second conductive path or the third conductive path is kept within a predetermined range of values during a write operation to provide a power supply level difference between the first power supply line and the second power supply line;
a fourth conductive path, coupled between the reference voltage and the first power supply line; and
a fifth conductive path, coupled between the reference voltage and the second power supply line wherein, in response to a write operation, the resistance in a selected one of the fourth and the fifth conductive paths is varied to provide a resistance.

### Claim 46 (depends on 45)

The elastic power header device of claim 45, wherein the resistance comprises a programmable resistance.

### Claim 47 (depends on 45)

The elastic power header device of claim 45, wherein the first to fifth conductive paths each comprise a device controlled to operate at an adjustable strength.

### Claim 48 (depends on 45)

The elastic power header device of claim 45, wherein the first to fifth conductive paths each comprise a transistor.

### Claim 49 (depends on 45)

The elastic power header device of claim 45, wherein the fourth and fifth conductive paths are attenuated during a write operation.

### Claim 50 (depends on 45)

The elastic power header device of claim 45, wherein the second and the third conductive paths are attenuated during a read operation.

### Claim 51 (depends on 45)

The elastic power header device of claim 45, further comprising a keeper circuit for limiting the difference between the first power supply line and the second power supply line.

### Claim 52

A computer-readable medium that includes a description of a circuit that implements an elastic power header device which includes a first power supply line and a second power supply line organized in a split power fashion in a memory device, where the circuit is adapted for use with a processor that executes operations that represent instructions, the instructions comprising:
configuring a first conductive path coupled between a reference voltage and both the first power supply line and the second power supply line, configured to provide a first voltage between the reference voltage and each one of the first power supply line and the second power supply line;
configuring a second conductive path, coupled between the reference voltage and the first power supply line;
configuring a third conductive path, coupled between the reference voltage and the second power supply line, wherein, in response to a read operation, a resistance in a selected one of the second conductive path or the third conductive path is kept within a predetermined range of values during a write operation to provide a power supply level difference between the first power supply line and the second power supply line;
configuring a fourth conductive path, coupled between the reference voltage and the first power supply line to provide a resistance in the first power supply line in response to a write operation; and
configuring a fifth conductive path, coupled between the reference voltage and the second power supply line to provide the resistance in the second power supply line in response to a write operation.

### Claim 53 (depends on 52)

The computer-readable medium as in claim 52, wherein the resistance comprises a programmable resistance.

### Claim 54 (depends on 52)

The computer-readable medium as in claim 52, wherein the first to fifth conductive paths each comprise a device controlled to operate at an adjustable strength during a read operation.

### Claim 55 (depends on 52)

The computer-readable medium as in claim 52, wherein the first to fifth conductive paths each comprise a transistor.

### Claim 56

A computer readable medium that includes a description of a memory device, where the memory device comprises:
a first power supply line;
a second power supply line;
a static random access memory (SRAM) cell comprising a first logic gate and a second logic gate that are cross-coupled, wherein the first power supply line supplies the first logic gate, and the second power supply line supplies the second logic gate; and
an elastic power header device connected between the reference voltage and each one of the first power supply line and the second power supply line wherein the elastic power header device is configured to provide, during a write operation of the first SRAM cell, different power supply levels on the first power supply line and the second power supply line and is configured to provide, during a read operation, a first resistance in the first power supply line and a second resistance in the second power supply line.

### Claim 57 (depends on 56)

The computer-readable medium as in claim 56, wherein at least one of the first and second resistances comprise a programmable resistance.

### Claim 58

A memory device comprising:
means for providing a reference voltage;
means for configuring a first power supply line and a second power supply line, and means for connecting a static random access memory (SRAM) cell comprising a first logic gate and a second logic gate that are cross-coupled, wherein the first power supply line supplies the first logic gate, and the second power supply line supplies the second logic gates; and
means for providing elastic power connected between the reference voltage and each one of the first power supply line and the second power supply line providing, during a write operation of the first SRAM cell, different power supply levels on the first power supply line and the second power supply line and, during a read operation, providing a first resistance in the first power supply line and a second resistance in the second power supply line.

### Claim 59 (depends on 58)

The memory device of claim 58, wherein at least one of the first and second resistances comprise a programmable resistance.