Fast and accurate sensing amplifier for low voltage semiconductor memory

A sensing circuit for a target memory cell, the target memory cell having a drain connected to a first node through a first selection circuit during a read operation involving the target memory cell, the target memory cell drawing a target memory cell current when activated during the read operation, comprising:

• a reference memory cell having a drain connected to a second node through a second selection circuit, the reference memory cell drawing a reference memory cell current when activated during the read operation;
• a first current mirror including first and second transistors, the target memory cell current outputted separately from drains of the first and second transistors to the first node and a third node;
• a second current mirror including third and fourth transistors, the target memory cell current outputted separately from the third node and a fourth node to drains of the third and fourth transistors, and sources of the third and fourth transistors connected to ground;
• a third current mirror including fifth and sixth transistors, the reference memory cell current outputted separately from drains of the fifth and sixth transistors to the second node and a fifth node;
• a fourth current mirror including seventh and eighth transistors, the reference memory cell current outputted separately from the fifth node and a sixth node to drains of the seventh and eighth transistors, and sources of the seventh and eighth transistors connected to ground;
• a ninth transistor and the first transistor forming a fifth current mirror, the target memory cell current outputted from a drain of the ninth transistor to the sixth node;
• a tenth transistor and the fifth transistor forming a sixth current mirror, the reference memory cell current outputted from a drain of the tenth transistor to the fourth node;
• and
• a sense amplifier having first and second inputs connected to the sixth and fourth nodes.

A method for sensing a charge level on a target memory cell, comprising the steps of:

• drawing a target cell current from a first node in response to selection of the target cell, the target cell current being dependent upon a charge level stored in the target cell;
• drawing a reference cell current from a second node in response to selection of the reference cell;
• generating into a third node a third current flow positively dependent upon the difference between the target cell current and the reference cell current;
• generating into a fourth node a fourth current flow negatively dependent upon the difference between the target cell current and the reference cell current;
• converting to a first voltage a current dependent upon the third current flow;
• converting to a second voltage a current dependent upon the fourth current flow;
• and
• amplifying a difference between the first and second voltages.