# US 2008/0186777 A1 · Relaxed metal pitch memory architectures

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- Number: US 2008/0186777 A1
- Document ID: US20080186777A1
- Status: Published application
- Kind: A1
- Application number: 11/703,487
- Filed: 2007-02-07
- Published: 2008-08-07
- Earliest claimed: 2007-02-07
- Assignees: Micron Technology, Inc.
- Inventors: Lyle D. Jones; Roger W. Lindsay; Kirk D. Prall
- Web page: https://patentgrep.com/patent/US20080186777A1

## CPC

- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- G11C 5/02: Disposition of storage elements, e.g. in the form of a matrix array
- H10B 41/30: characterised by the memory core region
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A relaxed metal pitch architecture may include a bit line and a first active area string and a second active area string. The bit line may be directly coupled to the first active area string and to the second active area string. The relaxed metal pitch architecture may be applied to a non-volatile memory structure.

## Claims

### Claim 1

A flash memory array comprising:
a bit line; and
a first active area string and a second active area string, wherein the bit line contacts the first active area string and the second active area string.

### Claim 2 (depends on 1)

The flash memory array of claim 1, wherein the flash memory array includes transistors connected to the bit line.

### Claim 3 (depends on 1)

The flash memory of claim 1, wherein the flash memory array includes less than three transistors connected to the bit line.

### Claim 4 (depends on 2)

The flash memory array of claim 2, wherein the bit line contacts a first contact, wherein the first contact contacts the first active area string, and wherein the first active area string includes a low threshold voltage region and a high voltage threshold region.

### Claim 5 (depends on 2)

The flash memory array of claim 2, wherein the bit line contacts a first contact and a second contact, wherein the first contact contacts the first active area string, wherein the first active area string includes a low threshold voltage region at a first side and a high voltage threshold region at a second side, wherein the second contact contacts the second active area string, and wherein the second active area string includes a low threshold voltage region at the second side and a high voltage threshold region at the first side.

### Claim 6 (depends on 1)

The flash memory array of claim 1, wherein the flash memory array includes only two transistors connected to the bit line.

### Claim 7 (depends on 1)

The flash memory array of claim 1, wherein the flash memory array includes different transistors connected to the bit line, further including select gates having different threshold voltages in the different transistors.

### Claim 8 (depends on 1)

The flash memory array of claim 1, wherein the flash memory array includes five select gates coupled to the bit line.

### Claim 9 (depends on 8)

The flash memory array of claim 8, wherein the bit line is a first bit line that contacts a first contact and a second contact, further including:
a second bit line coupled to the five select gates, wherein the second bit line contacts a third contact and a fourth contact, wherein the third contact contacts a third active area string, and the forth contact contacts a fourth active area string.

### Claim 10 (depends on 8)

The flash memory array of claim 8, wherein the bit line is a first bit line that contacts a first contact and a second contact, further including:
a second bit line coupled to the five select gates, wherein the second bit line contacts a third contact and a fourth contact, wherein the first active area string includes a sequence of accesses including medium-voltage and high-voltage at a first side and high-voltage and medium-voltage at a second side, and wherein the second active area string includes a sequence of accesses including low-voltage and medium-voltage at a first side and low-voltage and medium-voltage at a second side.

### Claim 11 (depends on 1)

The flash memory array of claim 1, wherein the bit line contacts a bit contact, and wherein the bit contact contacts the first active area string and the second active area string.

### Claim 12 (depends on 11)

The flash memory array of claim 11, wherein the first active area string includes a sequence of accesses including low threshold voltage region and high threshold voltage region at a first side and high threshold voltage region and low threshold voltage region at a second side, and wherein the second active area string includes a sequence of accesses including low threshold voltage region and high threshold voltage region at a first side and high threshold voltage region and low threshold voltage at a second side.

### Claim 13 (depends on 1)

The flash memory array of claim 1, wherein the flash memory array includes four select gates coupled to the bit line.

### Claim 14 (depends on 1)

The flash memory array of claim 1, wherein the flash memory array is a NAND flash memory array.

### Claim 15

A process comprising:
forming a first bit line over a semiconductive substrate including a first active area string and a second active area string, wherein the first bit line contacts the first active area string and the second active area string.

### Claim 16 (depends on 15)

The process of claim 15, wherein select gates are formed over the active area strings.

### Claim 17 (depends on 15)

The process of claim 15, further including:
forming three select gates below the first bit line, wherein the first active area string contacts a first contact and the first contact contacts the first bit line, and wherein the second active area string contacts a second contact and the second contact contacts the first bit line.

### Claim 18 (depends on 15)

The process of claim 15, wherein the first active area string is prepared by a process further including:
forming a low threshold voltage region; and
forming a high voltage threshold region.

### Claim 19 (depends on 18)

The process of claim 18, wherein the first active area string includes a gate oxide, the process further including:
forming the low threshold voltage region by etching the gate oxide; and
forming the high voltage threshold region

### Claim 20 (depends on 18)

The process of claim 18, wherein the first active area string includes a gate oxide, the process further including:
forming the low threshold voltage region by doping the semiconductive substrate differently than the high voltage threshold region.

### Claim 21 (depends on 18)

The process of claim 18, further including forming five select gates below the first bit line, wherein the first active area string contacts a first contact and the first contact contacts the first bit line, and wherein the second active area string contacts a second contact and the second contact contacts the first bit line.

### Claim 22 (depends on 15)

The process of claim 15, in the first active area string, the process further including:
forming a low threshold voltage region;
forming a medium voltage threshold region; and
forming a high voltage threshold region.

### Claim 23 (depends on 15)

The process of claim 15, in the first active area string, the process further including forming more than one threshold voltage region, wherein the more than one threshold voltage regions have different threshold voltages.

### Claim 24 (depends on 22)

The process of claim 22, wherein the first active area string includes a gate oxide, the process further including:
forming the low threshold voltage region by etching the gate oxide to a first amount; and
forming the medium voltage threshold region to a second amount that is greater than the first amount.

### Claim 25 (depends on 22)

The process of claim 22, wherein the first active area string includes a gate oxide, the process further including:
forming the low threshold voltage region by doping the semiconductive substrate differently than either of the medium voltage threshold region and the high voltage threshold region.

### Claim 26 (depends on 22)

The process of claim 22, further including forming four select gates below the first bit line, wherein the first active area string contacts a first contact and the first contact contacts the first bit line, and wherein the second active area string contacts the first contact.

### Claim 27

A computer system, comprising:
a processor;
a memory system coupled to the processor, including:
a bit line;
a first active area string and a second active area string, wherein the bit line contacts the first active area string and the second active area string; and
an input/output (I/O) circuit coupled to the processor and the memory system.

### Claim 28 (depends on 27)

The computer system of claim 27, wherein the first active area string is part of a NAND flash active area string.

### Claim 29 (depends on 27)

The computer system of claim 27, wherein the flash memory array includes select gates selected from a group consisting of three select gates, four select gates, and five select gates, coupled to the bit line.

### Claim 30 (depends on 27)

The computer system according to claim 27, wherein the processor is disposed in a host selected from a clock, a television, a cell phone, a personal computer, an automobile, an industrial control system, an aircraft, or a hand-held device.

### Claim 31 (depends on 27)

The computer system according to claim 27, wherein the memory system is disposed in a host selected from a clock, a television, a cell phone, a personal computer, an automobile, an industrial control system, an aircraft, or a hand-held device.