# US 2008/0186774 A1 · High-endurance memory device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2008/0186774 A1
- Document ID: US20080186774A1
- Status: Published application
- Kind: A1
- Application number: 11/701,886
- Filed: 2007-02-02
- Published: 2008-08-07
- Earliest claimed: 2007-02-02
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Yue-Der Chih
- Web page: https://patentgrep.com/patent/US20080186774A1

## CPC

- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory device includes a set of memory cells, each of which is capable of being selected to generate a sensing current depending on a logic state thereof, and a set of reference cells, each of which is capable of being selected to generate a reference current. A sense amplifier is coupled to the memory cells and the reference cells for comparing the sensing current with the reference current to generate a signal representing the logic state of the selected memory cell. The memory cells and the reference cells are subject to the same operation cycles, such that a difference between the sensing current and the reference current remains a constant.

## Claims

### Claim 1

A memory device comprising:
a set of memory cells, each of which is capable of being selected to generate a sensing current depending on a logic state thereof;
a set of reference cells, each of which is capable of being selected to generate a reference current, wherein the set of the memory cells and the reference cells are entirely erased before one or more of the memory cells are selected for a programming operation; and
a sense amplifier coupled to the memory cells and the reference cells for comparing the sensing current with the reference current to generate a signal representing the logic state of the selected memory cell,
wherein the memory cells that have not been selected for the programming operation are successively programmed before a page erase operation is executed, and
wherein the memory cells and the reference cells are subject to the same operation cycles, such that a difference between the sensing current and the reference current remains a constant.

### Claim 2 (depends on 1)

The memory device of claim 1 wherein the set of memory cells and the reference cells are addressed by a plurality of word lines and bit lines.

### Claim 3 (depends on 2)

The memory device of claim 2 wherein each of the word lines is connected to at least one corresponding reference cell.

### Claim 4 (depends on 2)

The memory device of claim 2 wherein the bit lines are connected to the sense amplifier.

### Claim 5 (depends on 1)

The memory device of claim 1 wherein the set of memory cells have the same operation cycles.

### Claim at position 6

6-7. (canceled)

### Claim 8 (depends on 1)

The memory device of claim 1 wherein the reference cells are programmed before the erase operation is executed.

### Claim 9 (depends on 1)

The memory device of claim 1 is a non-volatile memory device.

### Claim 10

A method for maintaining a sensing margin of a memory device, comprising:
selecting at least one memory cell from a set of memory cells to generate a sensing current depending on a logic state of the selected memory cell;
selecting at least one reference cell from a set of reference cells to generate a reference current;
erasing the memory cells and the reference cells entirely before one or more of the memory cells are selected for a programming operation;
programming the memory cells that have not been selected for the programming operation before a page erase operation is executed; and
comparing the sensing current with the reference current to generate a signal representing the logic state of the selected memory cell,
wherein the memory cells and the reference cells are subject to the same operation cycles, such that a difference between the sensing current and the reference current remains a constant.

### Claim 11 (depends on 10)

The method of claim 10 wherein the set of memory cells have the same operation cycles.

### Claim at position 11

12-13. (canceled)

### Claim 14 (depends on 10)

The method of claim 10 further comprising programming the reference cells before the page erase operation is executed.

### Claim 15 (depends on 10)

The method of claim 10 wherein the memory device is a non-volatile memory device.

### Claim 16

A memory device comprising:
a set of memory cells, each of which is capable of being selected to generate a sensing current depending on a logic state thereof;
a set of reference cells, each of which is capable of being selected to generate a reference current; and
a sense amplifier coupled to the memory cells and the reference cells for comparing the sensing current with the reference current to generate a signal representing the logic state of the selected memory cell,
wherein the set of the memory cells and the reference cells are entirely erased before one or more of the memory cells are selected for a programming operation,
wherein the reference cells and the memory cells that have not been selected for the programming operation are successively programmed before a page erase operation is executed, thereby maintaining a difference between the sensing current and the reference current at a constant value.

### Claim 17 (depends on 16)

The memory device of claim 16 wherein the set of memory cells and the reference cells are addressed by a plurality of word lines and bit lines.

### Claim 18 (depends on 17)

The memory device of claim 17 wherein each of the word lines is connected to at least one corresponding reference cell.

### Claim 19 (depends on 17)

The memory device of claim 17 wherein the bit lines are connected to the sense amplifier.

### Claim 20 (depends on 16)

The memory device of claim 16 is a non-volatile memory device.