# US 2008/0186769 A1 · Method for metal bit line arrangement

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- Number: US 2008/0186769 A1
- Document ID: US20080186769A1
- Status: Published application
- Kind: A1
- Application number: 11/703,115
- Filed: 2007-02-07
- Published: 2008-08-07
- Earliest claimed: 2007-02-07
- Assignees: Macronix International Co., Ltd.
- Inventors: Wen-Chiao Ho; Kuen-Long Chang; Chun-Hsiung Hung
- Web page: https://patentgrep.com/patent/US20080186769A1

## CPC

- G11C 7/18: Bit line organisation; Bit line lay-out
- G11C 7/02: with means for avoiding parasitic signals
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A method for metal bit line arrangement is applied to a virtual ground array memory having memory cell blocks. Each memory cell block has memory cells and m metal bit lines, wherein m is a positive integer. The method includes the following steps. First, one of the memory cells is selected as a target memory cell. When the target memory cell is being read, the metal bit line electrically connected to a drain of the target memory cell is a drain metal bit line, and the metal bit line electrically connected to a source is a source metal bit line. Next, a classification of whether the other metal bit lines are charged up when the target memory cell is being read is made. Thereafter, the m metal bit lines are arranged such that charged up metal bit lines are not adjacent to the source metal bit line.

## Claims

### Claim 1

A method for metal bit line arrangement being applied to a memory, which is a virtual ground array memory and has a plurality of memory cell blocks, each of the memory cell blocks has a plurality of memory cells, a plurality of select transistors and m metal bit lines, wherein m is a positive integer, the method comprising the steps of:
selecting one of the memory cells as a target memory cell, wherein when the target memory cell is being read, the metal bit line electrically connected to a drain of the target memory cell is defined as a drain metal bit line, and the metal bit line electrically connected to a source of the target memory cell is defined as a source metal bit line;
performing a classification of whether the other metal bit lines are charged up when the target memory cell is being read; and
arranging the m metal bit lines such that a charged up metal bit lines is not adjacent to the source metal bit line.

### Claim 2 (depends on 1)

The method according to claim 1, further comprising the step of:
arranging the m metal bit lines so that the drain metal bit line is not adjacent to the source metal bit line.

### Claim 3 (depends on 1)

The method according to claim 1, wherein:
the memory cell blocks further comprise a plurality of select transistors controlled by n select signals, wherein n is a positive integer; and
when the target memory cell is being read, a first select signal of the n select signals turns on a first select transistor of the select transistors so that the drain of the target memory cell is electrically connected to the drain metal bit line, and a second select signal of the n select signals turns on a second select transistor of the select transistors so that the source of the target memory cell is electrically connected to the source metal bit line.

### Claim 4 (depends on 3)

The method according to claim 3, wherein when the target memory cell is being read, the first select signal turns on a third select transistor of the select transistors, the second select signal turns on a fourth select transistor of the select transistors, then a first and a second metal bit line of the metal bit lines is charged up.

### Claim 5 (depends on 4)

The method according to claim 4, wherein the m metal bit lines are arranged so that the first metal bit line and the second metal bit line are not adjacent to the source metal bit line.

### Claim 6 (depends on 5)

The method according to claim 5, wherein m=8, a best arranged order of the eight metal bit lines comprises:
(metal bit line 2, metal bit line 0, metal bit line 1, metal bit line 3, metal bit line 5, metal bit line 7, metal bit line 6, metal bit line 4).

### Claim 7 (depends on 5)

The method according to claim 5, wherein m=8, a best arranged order of the eight metal bit lines comprises:
(metal bit line 2, metal bit line 0, metal bit line 1, metal bit line 7, metal bit line 6, metal bit line 4, metal bit line 5, metal bit line 3).