# US 2008/0186765 A1 · Semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2008/0186765 A1 - Document ID: US20080186765A1 - Status: Published application - Kind: A1 - Application number: 12/020,628 - Filed: 2008-01-28 - Published: 2008-08-07 - Earliest claimed: 2007-01-30 - Inventors: Takeshi KAMIGAICHI - Web page: https://patentgrep.com/patent/US20080186765A1 ## CPC - G11C 16/0483: {comprising cells having several storage transistors connected in series} - H10B 41/10: characterised by the top-view layout - H10B 41/40: characterised by the peripheral circuit region - H10B 41/48: with a tunnel dielectric layer also being used as part of the peripheral transistor - H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A semiconductor memory device according to one example includes a first cell transistor series including memory cell transistor connected in series, a first selecting transistor whose one terminal is connected to one terminal of the first cell transistor series, a second selecting transistor connected between the other terminal of the first selecting transistor and a bit line, and a third selecting transistor connected between the other terminal of the first cell transistor series and a source line. The first and second selecting transistors have a first conductive film, an inter-electrode insulating film and a second conductive film which are stacked on a semiconductor substrate. In one of the first and second selecting transistors, the first and second conductive films are connected to each other, and in the other transistor, the first and second conductive films are separated from each other. ## Claims ### Claim 1 A semiconductor memory device comprising: a first cell transistor series including memory cell transistor connected in series; a first selecting transistor whose one terminal is connected to one terminal of the first cell transistor series; a second selecting transistor connected between the other terminal of the first selecting transistor and a bit line; and a third selecting transistor connected between the other terminal of the first cell transistor series and a source line, wherein the first and second selecting transistors have a first conductive film, an inter-electrode insulating film and a second conductive film which are stacked on a semiconductor substrate, and in one of the first and second selecting transistors, the first and second conductive films are connected to each other, and in the other transistor, the first and second conductive films are separated from each other. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, wherein the first and second conductive films of the first selecting transistor are connected to each other, and the first and second conductive films of the second selecting transistor are separated from each other. ### Claim 3 (depends on 1) The semiconductor memory device according to claim 1, wherein the first and second conductive films of the first selecting transistor are separated from each other, and the first and second conductive films of the second selecting transistor are connected to each other. ### Claim 4 (depends on 1) The semiconductor memory device according to claim 1, wherein threshold voltages of the first and second selecting transistors are equal to each other. ### Claim 5 (depends on 1) The semiconductor memory device according to claim 1, wherein threshold voltages of the first and second selecting transistors are different from each other. ### Claim 6 (depends on 1) The semiconductor memory device according to claim 1, wherein an electric potential to be applied to the second conductive film of the first selecting transistor is different from an electric potential to be applied to the second conductive film of the second selecting transistor. ### Claim 7 (depends on 1) The semiconductor memory device according to claim 1, wherein the first and second selecting transistors are connected in series via a source/drain diffusion layer in the semiconductor substrate. ### Claim 8 (depends on 1) The semiconductor memory device according to claim 1, wherein the first cell transistor series constitutes a NAND string. ### Claim 9 A semiconductor memory device comprising: a first cell transistor series and a second cell transistor series arranged adjacently in a row direction, each having memory cell transistors connected in series; a first selecting transistor whose one terminal is connected to one terminal of the first cell transistor series; a second selecting transistor connected between the other terminal of the first selecting transistor and a first bit line; a third selecting transistor connected between the other terminal of the first cell transistor series and a source line; a fourth selecting transistor whose one terminal is connected to one terminal of the second cell transistor series; a fifth selecting transistor connected between the other terminal of the fourth selecting transistor and a second bit line; and a sixth selecting transistor connected between the other terminal of the second cell transistor series and the source line, wherein the first, second, fourth and fifth selecting transistors have a first conductive film, an inter-electrode insulating film and a second conductive film which are stacked on a semiconductor substrate, and in the first and fifth selecting transistors, the first and second conductive films are connected to each other, and in the second and fourth selecting transistors, the first and second conductive films are separated from each other. ### Claim 10 (depends on 9) The semiconductor memory device according to claim 9, wherein the second conductive films of the first and fourth selecting transistors are connected to each other, and the second conductive films of the second and fifth selecting transistors are connected to each other. ### Claim 11 (depends on 10) The semiconductor memory device according to claim 10, wherein threshold voltages of the first, second, fourth and fifth selecting transistors are equal to one another. ### Claim 12 (depends on 11) The semiconductor memory device according to claim 11, wherein a first electric potential to be applied to the second conductive films of the first and fourth selecting transistors is different from a second electric potential to be applied to the second conductive films of the second and fifth selecting transistors. ### Claim 13 (depends on 12) The semiconductor memory device according to claim 12, wherein when the first electric potential is higher than the second electric potential, the first, fourth and fifth selecting transistors are turned on, and the second selecting transistor is turned off. ### Claim 14 (depends on 13) The semiconductor memory device according to claim 13, wherein when the first electric potential is higher than the second electric potential, reading/writing is executed on one selecting cell in the second cell transistor series. ### Claim 15 (depends on 12) The semiconductor memory device according to claim 12, wherein when the second electric potential is higher than the first electric potential, the first, second and fifth selecting transistors are turned on, and the fourth selecting transistor is turned off. ### Claim 16 (depends on 15) The semiconductor memory device according to claim 15, wherein when the second electric potential is higher than the first electric potential, reading/writing is executed on one selecting cell in the first cell transistor series. ### Claim 17 (depends on 10) The semiconductor memory device according to claim 10, wherein threshold voltages of the first and fourth selecting transistors are equal to each other, threshold voltages of the second and fifth selecting transistors are equal to each other, threshold voltages of the first and second selecting transistors are different from each other, and threshold voltages of the fourth and fifth selecting transistors are different from each other. ### Claim 18 (depends on 17) The semiconductor memory device according to claim 17, wherein a first electric potential to be applied to the second conductive films of the first and fourth selecting transistors is different from a second electric potential to be applied to the second conductive films of the second and fifth selecting transistors. ### Claim 19 (depends on 9) The semiconductor memory device according to claim 9, wherein the first and second selecting transistors are connected in series via a first source/drain diffusion layer in the semiconductor substrate, and the fourth and fifth selecting transistors are connected in series via a second source/drain diffusion layer in the semiconductor substrate. ### Claim 20 (depends on 9) The semiconductor memory device according to claim 9, wherein the first cell transistor series and the second cell transistor series constitute NAND strings, respectively.