# US 2008/0186764 A1 · Nor architecture memory and operation method thereof

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- Number: US 2008/0186764 A1
- Document ID: US20080186764A1
- Status: Published application
- Kind: A1
- Application number: 11/672,063
- Filed: 2007-02-07
- Published: 2008-08-07
- Earliest claimed: 2007-02-07
- Assignees: Macronix International Co., Ltd.
- Inventors: Yung-Feng Lin
- Web page: https://patentgrep.com/patent/US20080186764A1

## CPC

- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
- G11C 16/32: Timing circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An operation method of a NOR architecture memory includes the following steps. First, a target word line is selected. Next, an initial enable voltage is applied to the target word line to charge the target word line. Then, the initial enable voltage is switched to a target voltage after a pre-charge time to make the target word line be charged to the target voltage. The initial enable voltage is higher than the target voltage. The pre-charge time corresponds to the initial enable voltage and the target voltage.

## Claims

### Claim 1

An operation method for a NOR architecture memory, the method comprising the steps of:
selecting a target word line;
applying an initial enable voltage to the target word line to charge the target word line; and
switching the initial enable voltage, which is higher than a target voltage, to the target voltage after a pre-charge time to make the target word line be charged to the target voltage,
wherein the pre-charge time corresponds to the initial enable voltage and the target voltage.

### Claim 2 (depends on 1)

The method according to claim 1, wherein in the pre-charge time, the target word line is charged to a pre-charge voltage slightly lower than the target voltage.

### Claim 3 (depends on 2)

The method according to claim 2, wherein when the target word line is charged to the target voltage, a row of memory cells corresponding to the target word line is enabled.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the NOR architecture memory is a non-volatile memory.

### Claim 5 (depends on 4)

The method according to claim 4, the NOR architecture memory is a flash memory.

### Claim 6

An NOR architecture memory, comprising:
a NOR architecture memory cell array having a plurality of memory cells arranged in an array having m rows and n columns, m and n being positive integers;
m word lines respectively corresponding to the m rows of memory cells, wherein each of the word lines is coupled to n gates of the corresponding row of memory cells;
a row decoder for selecting one of the word lines as a target word line; and
a control circuit, which is coupled to the row decoder, applies an initial enable voltage to the target word line to charge the target word line, and then switches the initial enable voltage to a target voltage after a pre-charge time to make the target word line be charged to the target voltage, wherein the initial enable voltage is higher than the target voltage.

### Claim 7 (depends on 6)

The memory according to claim 6, wherein the pre-charge time corresponds to the initial enable voltage and the target voltage.

### Claim 8 (depends on 7)

The memory according to claim 7, wherein the target word line is charged to a pre-charge voltage, which is slightly lower than the target voltage, in the pre-charge time.

### Claim 9 (depends on 8)

The memory according to claim 8, wherein the control circuit comprises:
a pre-charge control unit controlled by an enable reading signal to output a switching signal; and
a multiplexer having a first input terminal coupled to the initial enable voltage, a second input terminal coupled to the target voltage, and a control terminal for receiving the switching signal, wherein the multiplexer decides to output the initial enable voltage or the target voltage to the row decoder according to the switching signal.

### Claim 10 (depends on 9)

The memory according to claim 9, wherein the pre-charge control unit comprises:
a first resistor having a first terminal coupled to a first voltage;
a second resistor having a first terminal coupled to a second terminal of the first resistor;
a first transistor having a first terminal coupled to a second terminal of the second resistor, a second terminal coupled to a second voltage, and a control terminal for receiving the enable reading signal;
a dummy word line, which is the same as one of the word lines, and has a first terminal coupled to the control terminal of the first transistor;
a comparator having a first input terminal coupled to a second terminal of the dummy word line, a second input terminal coupled to the second terminal of the first resistor, and an output terminal for outputting the switching signal;
an inverter having an input terminal for receiving the enable reading signal; and
a second transistor having a first terminal coupled to the first input terminal of the comparator, a second terminal coupled to the second voltage, and a control terminal coupled to an output terminal of the inverter, wherein a ratio of a resistance of the second resistor to a sum of a resistance of the first resistor and a resistance of the second resistor is a ratio of the pre-charge voltage to the initial enable voltage.

### Claim 11 (depends on 10)

The memory according to claim 10, wherein the first transistor and the second transistor are NMOS field effect transistors.

### Claim 12 (depends on 11)

The memory according to claim 11, wherein the first voltage is an operation voltage and the second voltage is a ground voltage.

### Claim 13 (depends on 6)

The memory according to claim 6, the NOR architecture memory is a non-volatile memory.

### Claim 14 (depends on 13)

The memory according to claim 13, the NOR architecture memory is a flash memory.