# US 2008/0186755 A1 · Memory cell device and programming methods > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2008/0186755 A1 - Document ID: US20080186755A1 - Status: Published application - Kind: A1 - Application number: 11/777,195 - Filed: 2007-07-12 - Published: 2008-08-07 - Earliest claimed: 2007-02-05 - Assignees: Macronix International Co., Ltd. - Inventors: Hsiang Lan Lung; Yi-Chou Chen - Web page: https://patentgrep.com/patent/US20080186755A1 ## CPC - G11C 13/0061: {Timing circuits or methods} - G11C 11/56: using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency - G11C 11/5678: {using amorphous/crystalline phase transition storage elements} - G11C 13/0004: {comprising amorphous/crystalline phase transition cells} - G11C 13/0069: {Writing or programming circuits or methods} - G11C 2013/0092: {Write characterized by the shape, e.g. form, length, amplitude of the write pulse} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory device including a memory cell comprising phase change material is described along with methods for programming the memory device. A method for programming disclosed herein includes determining a data value for the memory cell, and applying a pulse pair to store the data value. The pulse pair includes an initial pulse having a pulse shape adapted to preset the phase change material in the memory cell to a normalizing resistance state, and a subsequent pulse having a pulse shape adapted to set the phase change material from the normalizing resistance state to a resistance corresponding to the determined data value. ## Claims ### Claim 1 A method for programming a memory cell comprising phase change material, the method comprising: determining a data value for the memory cell; and applying a pulse pair to store the data value, the pulse pair including an initial normalizing pulse having a pulse shape adapted to preset the phase change material in the memory cell to a normalizing resistance state and a subsequent pulse having a pulse shape adapted to set the phase change material in the memory cell from the normalizing resistance state to a resistance corresponding to the determined data value. ### Claim 2 (depends on 1) The method of claim 1, wherein the memory cell is adapted for storing 2 bits, and including applying a first pulse pair if the determined data value is 00, a second pulse pair if the determined data value is 01, a third pulse pair if the determined data value is 10, and a fourth pulse pair if the determined data value is 11. ### Claim 3 (depends on 1) The method of claim 1, including: applying a first pulse pair if the determined data value is a first data value, the first pulse pair comprising a first pulse having a pulse shape adapted to preset the phase change material to the normalizing resistance state, and a second pulse having a pulse shape adapted to set the phase change material from the normalizing resistance state to a resistance corresponding to the first data value; and applying a second pulse pair if the determined data value is a second data value, the second pulse pair comprising a third pulse having a pulse shape adapted to preset the phase change material to the normalizing resistance state, and a fourth pulse having a pulse shape adapted to set the phase change material from the normalizing resistance state to a resistance corresponding to the second data value, wherein the pulse shape of the third pulse is similar to the pulse shape of the first pulse. ### Claim 4 (depends on 3) The method of claim 3, wherein the fourth pulse has a pulse length of time larger than that of the second pulse. ### Claim 5 (depends on 3) The method of claim 3, wherein the second pulse is applied at least about 5 ns after the first pulse presets the phase change material to the normalizing resistance state. ### Claim 6 (depends on 3) The method of claim 3, wherein the second pulse is applied at least about 1 ns after the first pulse presets the phase change material to the normalizing resistance state. ### Claim 7 A method for programming a memory cell comprising phase change material, the method comprising: determining a data value for the memory cell; applying a reset pulse if the determined data value is a first data value, the reset pulse having a pulse shape adapted to cause a transition of an active region into an amorphous phase, thereby setting the phase change material to a resistance corresponding to the first data value; applying a first pulse pair if the determined data value is a second data value, the first pulse pair comprising a first pulse having a pulse shaped adapted to cause a transition of the active region into an amorphous phase, and a second pulse having a pulse shape adapted to cause of transition of a portion of the active region into a crystalline phase, thereby setting the phase change material to a resistance corresponding to the second data value; and applying a second pulse pair if the determined data value is a third data value, the second pulse pair comprising a third pulse having a pulse shape adapted to cause a transition of the active region into an amorphous phase, and a fourth pulse having a pulse shape adapted to cause a transition of a portion of the active region into a crystalline phase, thereby setting the phase change material to a resistance corresponding to the third data value. ### Claim 8 A memory device comprising: a memory cell comprising phase change material; and bias circuitry adapted to apply a bias arrangement to the memory cell for storing a data value; wherein the bias arrangement for storing the data value comprises a pulse pair, the pulse pair including an initial pulse having a pulse shape adapted to preset the phase change material in the memory cell to a normalizing resistance state and a subsequent pulse having a pulse shape adapted to set the phase change material in the memory cell from the normalizing resistance state to a resistance corresponding to the data value. ### Claim 9 (depends on 8) The memory device of claim 8, wherein the memory cell is adapted for storing 2 bits, and including the bias arrangement comprising a first pulse pair if the data value is 00, the bias arrangement comprising a second pulse pair if the data value is 01, the bias arrangement comprising a third pulse pair if the data value is 10, and the bias arrangement comprising a fourth pulse pair if the data value is 11. ### Claim 10 (depends on 8) The memory device of claim 8, including: the bias arrangement comprising a first pulse pair if the data value is a first data value, the first pulse pair comprising a first pulse having a pulse shape adapted to preset the phase change material to the normalizing resistance state, and a second pulse having a pulse shape adapted to set the phase change material from the normalizing resistance state to a resistance corresponding to the first data value; and the bias arrangement comprising a second pulse pair if the data value is a second data value, the second pulse pair comprising a third pulse having a pulse shape adapted to preset the phase change material to the normalizing resistance state, and a fourth pulse having a pulse shape adapted to set the phase change material from the normalizing resistance state to a resistance corresponding to the second data value, wherein the pulse shape of the third pulse is similar to the pulse shape of the first pulse. ### Claim 11 (depends on 10) The device of claim 10, wherein the fourth pulse has a pulse length of time larger than that of the second pulse. ### Claim 12 (depends on 10) The device of claim 10, wherein the second pulse is applied at least about 5 ns after the first pulse presets the phase change material to the normalizing resistance state. ### Claim 13 (depends on 10) The device of claim 10, wherein the second pulse is applied at least about 1 ns after the first pulse presets the phase change material to the normalizing resistance state. ### Claim 14 A memory device comprising: a memory cell comprising phase change material; and bias circuitry adapted to apply a bias arrangement to the memory cell for storing a data value; wherein the bias arrangement comprises a reset pulse if the data value is a first data value, the reset pulse having a pulse shape adapted to cause a transition of an active region into an amorphous phase, thereby setting the phase change material to a resistance corresponding to the first data value; wherein the bias arrangement comprises a first pulse pair if the data value is a second data value, the first pulse pair comprising a first pulse having a pulse shaped adapted to cause a transition of the active region into an amorphous phase, a second pulse having a pulse shape adapted to cause a transition of a portion of the active region into a crystalline phase, thereby setting the phase change material to a resistance corresponding to the second data value; wherein the bias arrangement comprises a second pulse pair if the data value is a third data value, the second pulse pair comprising a third pulse having a pulse shape adapted to cause a transition of the active region into an amorphous phase, and a fourth pulse having a pulse shape adapted to cause a transition of a portion of the active region into a crystalline phase, thereby setting the phase change material to a resistance corresponding to the third data value.