# US 2008/0186652 A1 · Multilayer chip capacitor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2008/0186652 A1 - Document ID: US20080186652A1 - Status: Published application - Kind: A1 - Application number: 11/987,835 - Filed: 2007-12-05 - Published: 2008-08-07 - Earliest claimed: 2007-02-05 - Assignees: Samsung Electro-Mechanics Co., Ltd. - Inventors: Byoung Hwa Lee; Sung Kwon Wi; Hae Suk Chung; Dong Seok Park; Sang Soo Park; Min Cheol Park - Web page: https://patentgrep.com/patent/US20080186652A1 ## CPC - H01G 4/30: Stacked capacitors (H01G4/33 takes precedence) - H01G 4/012: Form of non-self-supporting electrodes - H01G 4/232: electrically connecting two or more layers of a stacked or rolled capacitor - H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10) ## Abstract A multilayer chip capacitor includes: a capacitor body having first and second side surfaces and a bottom surface; a plurality of first and second internal electrodes in the capacitor body; first and second external electrodes having a first polarity and formed on the first and second side surfaces, respectively, to cover a respective lower edge of the side surfaces and to partially extend to the bottom surface; and a third external electrode having a second polarity and formed on the bottom surface. The internal electrodes are disposed in perpendicular to the bottom surface. Each of the first internal electrodes has a first lead drawn to the first side and bottom surfaces and a second lead drawn to the second side and bottom surfaces. Each of the second internal electrodes has a third lead drawn to the bottom surface. ## Claims ### Claim 1 A multilayer chip capacitor comprising: a capacitor body formed by laminating a plurality of dielectric layers and having first and second side surface facing each other, a top surface and a bottom surface; a plurality of first and second internal electrodes alternately disposed in the capacitor body with each of the dielectric layers interposed therebetween; a first external electrode of a first polarity formed on the first side surface to cover a lower edge of the first side surface and to partially extend to the bottom surface; a second external electrode of the first polarity formed on the second side surface to cover a lower edge of the second side surface and to partially extend to the bottom surface; and a third external electrode of a second polarity formed on the bottom surface between the first and second external electrodes, wherein the first and second internal electrodes are disposed in perpendicular to the bottom surface of the capacitor body, wherein each of the first internal electrodes has a first lead drawn to the first side surface and the bottom surface and a second lead drawn to the second side surface and the bottom surface, and each of the second internal electrodes has a third lead drawn to the bottom surface between the first and second leads, and wherein the first to third leads are in contact with the first to third external electrodes through the entire length of the edge portions of the respective leads exposed to outer surfaces of the capacitor body to be connected to the first to third external electrodes, respectively. ### Claim 2 (depends on 1) The multilayer chip capacitor of claim 1, wherein the first external electrode is formed to cover upper and lower edges of the first side surface of the capacitor body and to partially extend to the top surface and the bottom surface of the capacitor body, and wherein the second external electrode is formed to cover upper and lower edges of the second side surface of the capacitor body and to partially extend to the top surface and the bottom surface of the capacitor body ### Claim 3 (depends on 1) The multilayer chip capacitor of claim 1, wherein a width of a portion of the first lead drawn to the bottom surface of the capacitor body is equal to a width of a portion of the second lead drawn to the bottom surface of the capacitor body. ### Claim 4 (depends on 3) The multilayer chip capacitor of claim 3, wherein a width of the third lead is larger than the width of the portion of the first lead drawn to the bottom surface. ### Claim 5 (depends on 1) The multilayer chip capacitor of claim 1, wherein a lamination direction length of the capacitor body is smaller than a distance between the first side surface and the second side surface. ### Claim 6 (depends on 5) The multilayer chip capacitor of claim 5, wherein a width of a portion of the first lead drawn to the bottom surface of the capacitor body is equal to a width of a portion of the second lead drawn to the bottom surface of the capacitor body, and wherein a width ratio of a width of the third lead to the width of the portion of the first lead drawn to the bottom surface is 1.38 or more. ### Claim 7 (depends on 6) The multilayer chip capacitor of claim 6, wherein the width ratio ranges from 1.38 to 7. ### Claim 8 (depends on 1) The multilayer chip capacitor of claim 1, wherein a lamination direction length of the capacitor body is larger than a distance between the first side surface and the second side surface. ### Claim 9 (depends on 8) The multilayer chip capacitor of claim 8, wherein a width of a portion of the first lead drawn to the bottom surface of the capacitor body is equal to a width of a portion of the second lead drawn to the bottom surface of the capacitor body, and wherein a width ratio of a width of the third lead to the width of the portion of the first lead drawn to the bottom surface is 2 or more. ### Claim 10 (depends on 9) The multilayer chip capacitor of claim 9, wherein the width ratio ranges from 2 to 7. ### Claim 11 (depends on 1) The multilayer chip capacitor of claim 1, further comprising a fourth external electrode of the second polarity formed on the top surface of the capacitor body between the first external electrode and second external electrode, wherein the first lead is formed to be drawn to the first side surface, the bottom surface and the top surface, and the second lead is formed to be drawn to the second side surface, the bottom surface and the top surface, wherein the first external electrode is formed to cover upper and lower edges of the first side surface and to partially extend to the top surface and the bottom surface, and the second external electrode is formed to cover upper and lower edges of the second side surface and to partially extend to the top surface and the bottom surface, wherein each of the second internal electrodes further includes a fourth lead formed between the first and second leads to be drawn to the top surface and to be connected to the fourth external electrode, and wherein the fourth lead is in contact with the fourth external electrode through the entire edge portion of the fourth lead exposed to the bottom surface to be connected to the fourth external electrode. ### Claim 12 (depends on 11) The multilayer chip capacitor of claim 11, wherein internal and external structures of the multilayer chip capacitor have up-down symmetry. ### Claim 13 A multilayer chip capacitor comprising: a capacitor body formed by laminating a plurality of dielectric layers and having a bottom surface to be mounted on a circuit board; a plurality of internal electrodes disposed in perpendicular to the bottom surface in the capacitor body with each of the dielectric layers interposed therebetween; a first external electrode of a first polarity formed on a first side surface of the capacitor body to partially extend to the bottom surface; a second external electrode of the first polarity formed on a second side surface opposite to the first side surface to partially extend to the bottom surface; and a third external electrode of a second polarity formed on the bottom surface between the first and second external electrodes, wherein a width of the third external electrode is larger than a width of a portion of the first external electrode extending to the bottom surface and a width of a portion of the second external electrode extending to the bottom surface. ### Claim 14 (depends on 13) The multilayer chip capacitor of claim 13, wherein the first and second external electrodes are formed symmetrically in a mirror-like shape, and the widths of the first and second external electrodes extending to the bottom surface are equal to each other. ### Claim 15 A multilayer chip capacitor comprising: a capacitor body formed by laminating a plurality of dielectric layers and having a bottom surface to be mounted on a circuit board and first and second side surfaces facing each other; a plurality of first-polarity and second-polarity internal electrodes alternately disposed to face each other in the capacitor body with each of the dielectric layers interposed therebetween and disposed in perpendicular to the bottom surface of the capacitor body; first and second external electrodes formed on the first and second side surfaces, respectively, to partially extend to the bottom surface and to be electrically connected to the first-polarity internal electrodes; and a third external electrode formed on the bottom surface between the first and second external electrodes to be connected to the second-polarity internal electrodes, wherein two current loops are generated by currents flowing from the first and second external electrodes to the third external electrode. ### Claim 16 (depends on 15) The multilayer chip capacitor of claim 15, wherein the first-polarity internal electrodes have first internal electrode patterns connected to both the first and second external electrodes, and wherein the second-polarity internal electrodes have second internal electrode patterns connected to the third external electrode. ### Claim 17 (depends on 15) The multilayer chip capacitor of claim 15, wherein the first-polarity internal electrodes have first internal electrode patterns connected to only the first external electrode and second internal electrode patterns connected to only the second external electrode, the first and second internal electrode patterns being alternately disposed in a lamination direction, and wherein the second-polarity internal electrodes have third internal electrode patterns connected to only the third external electrode. ### Claim 18 (depends on 15) The multilayer chip capacitor of claim 15, further comprising a fourth external electrode of the second polarity formed on the top surface of the capacitor body between the first external electrode and the second external electrode. ### Claim 19 (depends on 18) The multilayer chip capacitor of claim 18, wherein each of the first-polarity internal electrodes is formed to have an “H”-shaped electrode pattern to be connected to the first and second external electrodes, and wherein each of the second-polarity internal electrodes is formed to have a “+”-shaped electrode pattern to be connected to the third and fourth external electrodes. ### Claim 20 (depends on 18) The multilayer chip capacitor of claim 18, wherein the first-polarity internal electrodes are formed by alternately and repeatedly disposing two “T”-shaped electrode patterns in opposite directions to be alternately connected to the first external electrode and the second external electrode, and wherein each of the second-polarity internal electrodes is formed to have a “+”-shaped electrode pattern. ### Claim 21 A multilayer chip capacitor comprising: a capacitor body formed by laminating a plurality of dielectric layers and having a bottom surface to be mounted on a circuit board and first and second side surfaces facing each other; a plurality of first-polarity and second-polarity internal electrodes alternately disposed to face each other in the capacitor body with each of the dielectric layers interposed therebetween, the first-polarity and second-polarity internal electrodes being disposed in perpendicular to the bottom surface of the capacitor body; first and second external electrodes formed on the first and second side surfaces to extend to the bottom surface and to be electrically connected to the first-polarity internal electrodes; and a third external electrode formed on the bottom surface between the first and second external electrodes to be connected to the second-polarity internal electrodes, wherein each of the first-polarity internal electrodes has a first-polarity main portion and a first-polarity lead drawn from the first-polarity main portion to the bottom surface and one side surface to be connected to one of the first and second external electrodes, wherein each of the second-polarity internal electrodes has a second-polarity main portion and a second-polarity lead drawn from the second-polarity main portion to the bottom surface to be connected to the third external electrode, wherein a distance from the first-polarity main portion to the bottom surface is equal to a distance from the second-polarity main portion to the bottom surface, and wherein ESL of 100 pH or less is obtained by adjusting a gap G between adjacent first-polarity lead and the second-polarity lead, a distance M from the first-polarity main portion to the bottom surface, the number N of internal electrodes in the capacitor body, and a lead width ratio W2/W1 of a width W2 of the second-polarity lead to a width W1 of a portion of the first-polarity drawn to the bottom surface. ### Claim 22 (depends on 21) The multilayer chip capacitor of claim 21, wherein each of the first-polarity internal electrodes has two of the first-polarity leads to be connected to the first and second external electrodes, and wherein the two first-polarity leads are a first lead drawn to the bottom surface and the first side surface to be connected to the first external electrode and a second lead drawn to the bottom surface and the second side surface to be connected to the second external electrode. ### Claim 23 (depends on 21) The multilayer chip capacitor of claim 21, wherein the first-polarity internal electrodes have first internal electrode patterns connected to only the first external electrode and second internal electrode patterns connected to only the second external electrode, the first and second internal electrode patterns being alternately disposed in a lamination direction, wherein the second-polarity internal electrodes have third internal electrode patterns connected to only the third external electrode, wherein each of the first internal electrode patterns has a first lead drawn to the bottom surface and the first side surface to be connected to the first external electrode, and wherein each of the second internal electrode patterns has a second lead drawn to the bottom surface and the second side surface to be connected to the second external electrode. ### Claim 24 (depends on 21) The multilayer chip capacitor of claim 21, further comprising a fourth external electrode of the second polarity formed on the top surface between the first external electrode and the second external electrode. ### Claim 25 (depends on 24) The multilayer chip capacitor of claim 24, wherein each of the first-polarity internal electrodes is formed to have an “H”-shaped electrode pattern to be connected to the first and second external electrodes, and wherein each of the second-polarity internal electrodes is formed to have a “+”-shaped electrode pattern to be connected to the third and fourth external electrodes. ### Claim 26 (depends on 24) The multilayer chip capacitor of claim 24, wherein the first-polarity internal electrodes are formed by alternately and repeatedly disposing two “T”-shaped electrode patterns in opposite directions to be alternately connected to the first external electrode and the second external electrode, and wherein each of second-polarity internal electrodes is formed to have a “+”-shaped electrode pattern to be connected to the third and fourth external electrodes. ### Claim 27 A multilayer chip capacitor comprising: a capacitor body formed by laminating a plurality of dielectric layers and having a bottom surface to be mounted on a circuit board, first and second side surfaces facing each other, and third and fourth side surfaces facing each other; a plurality of first-polarity and second-polarity internal electrodes alternately disposed to face each other in the capacitor body with each of the dielectric layers interposed therebetween, the first-polarity and second-polarity internal electrodes being disposed in parallel to the bottom surface of the capacitor body; a first external electrode formed on the first side surface to partially extend to the third and fourth side surfaces and to be electrically connected to the first-polarity internal electrodes; a second external electrode formed on the second side surface to partially extend to the third and fourth side surfaces and to be electrically connected to the first-polarity internal electrodes; and a third external electrode formed on the third and fourth side surfaces between the first and second side surfaces to be electrically connected to the second-polarity internal electrodes; wherein each of the first-polarity internal electrodes has a first-polarity lead drawn to the third and fourth side surfaces and one of the first and second side surfaces to be connected to one of the first and second external electrodes, wherein each of the second-polarity internal electrodes has two second-polarity leads drawn to the third and fourth side surfaces to be connected to the third external electrode, and wherein a width ratio of a width of the second-polarity lead to a width of a portion of the first-polarity lead drawn to the third side surface is 1.43 or more. ### Claim 28 (depends on 27) The multilayer chip capacitor of claim 27, wherein each of the first-polarity internal electrodes is formed to have an “H”-shaped electrode pattern to be connected to the first and second external electrodes, and wherein each of the second-polarity internal electrodes is formed to have a “+”-shaped electrode pattern to be connected to the third external electrode. ### Claim 29 (depends on 27) The multilayer chip capacitor of claim 27, wherein the first-polarity internal electrodes are formed by alternately and repeatedly disposing two “T”-shaped electrode patterns in opposite directions to be alternately connected to the first external electrode and the second external electrode, and wherein each of second-polarity internal electrodes is formed to have a “+”-shaped electrode pattern to be connected to the third external electrode.