# US 2008/0186295 A1 · Data driver and flat panel display using the same

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- Number: US 2008/0186295 A1
- Document ID: US20080186295A1
- Status: Published application
- Kind: A1
- Application number: 12/068,105
- Filed: 2008-02-01
- Published: 2008-08-07
- Earliest claimed: 2007-02-02
- Assignees: Samsung Mobile Display Co., Ltd.
- Inventors: Byong-Deok Choi
- Web page: https://patentgrep.com/patent/US20080186295A1

## CPC

- G09G 3/3688: {suitable for active matrices only}
- G09G 3/3291: in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
- G09G 2310/0259: with use of an analog or digital ramp generator in the column driver or in the pixel circuit
- G09G 2310/027: Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

Disclosed is a data driver including a holding latch and a digital-analog converter. The data driver includes a holding latch for storing data and for generating a counting signal corresponding to the value of the stored data. A digital-analog converter receives ramp pulses from an external apparatus, and controls supply time of the ramp pulses according to the counting signals. A voltage level of a data signal that is supplied to a pixel unit of a flat panel display is determined by the output of the digital-analog converter.

## Claims

### Claim 1

A data driver generating a data signal to drive a flat panel display, the data driver comprising:
a holding latch for receiving data for the data driver and for receiving a control signal, the holding latch storing the data and outputting a counting signal that is generated according to the value of the data; and
a digital-analog converter for receiving a ramp pulse and the counting signal, the digital-analog converter determining a voltage level of the data signal by cropping the ramp pulse during a period for which the counting signal is supplied.

### Claim 2 (depends on 1)

The data driver as claimed in claim 1, wherein the holing latch includes a plurality of logic units, each of the logic units receiving, through an input terminal, a bit value the data, each of the logic units operating as a D flip-flop or a T flip-flop depending on the control signal, each of the logic units having an output terminal and an inversion output terminal.

### Claim 3 (depends on 2)

The data driver as claimed in claim 2, wherein each of the logic units comprises:
a flip-flop unit;
a first logic gate, a first input terminal of the first logic gate being coupled to an output terminal of the flip-flop unit, a second input terminal of the first logic gate being coupled to the input terminal of the each of the logic units; and
a first demultiplexer being coupled to an output terminal of the first logic gate and the input terminal of the each of the logic units, the first demultiplexer outputting an output from the first logic gate or an output from the input terminal of the each of the logic units depending on a polarity of the control signal, an output terminal of the first demultiplexer being coupled to the flip-flop unit.

### Claim 4 (depends on 3)

The data driver as claimed in claim 3, wherein the first demultiplexer is switched to output the output from the input terminal of the each of the logic units if the control signal includes a second polarity.

### Claim 5 (depends on 4)

The data driver as claimed in claim 4, wherein the each of the logic unit stores the bit value of the data if the control signal includes the second polarity.

### Claim 6 (depends on 3)

The data driver as claimed in claim 3, wherein the first demultiplexer is switched to output the output from the output terminal of the first logic gate if the control signal includes a first polarity.

### Claim 7 (depends on 6)

The data driver as claimed in claim 6, wherein the holding latch outputs a counting signal if the control signal includes the first polarity.

### Claim 8 (depends on 7)

The data driver as claimed in claim 7, wherein the holding latch stops outputting the counting signal if all bit values of the data have “0.”

### Claim 9 (depends on 3)

The data driver as claimed in claim 3, wherein the first logic gate includes an exclusive OR gate.

### Claim 10 (depends on 3)

The data driver as claimed in claim 3, wherein the holding latch comprises:
a second switch coupled to an input terminal of a first one of the logic units, the input terminal of the first one of the logic units receiving the bit value through the second switch;
a first-first switch coupled between the inversion output terminal of the first one of the logic units and an input terminal of a second one of the logic units, the first-first switch being turned on if the control signal includes a first polarity;
a second-first switch coupled between the inversion output terminal of the second one of the logic units and an input terminal of a third one of the logic units, the second-first switch being turned on if the control signal includes a first polarity;
a first-second logic gate coupled between the inversion output terminal of the first one of the logic units and the first-first switch;
a second-second logic gate coupled between the inversion output terminal of the second one of the logic units and the second-first switch;
a first-third logic gate coupled to an output terminal of the first one of the logic units and to an output terminal of a fourth one of the logic units;
a second-third logic gate coupled to the output terminal of the second one of the logic units and to the output terminal of the third one of the logic units; and
a fourth logic gate coupled to an output terminal of the first-third logic gate and to an output terminal of the second-third logic gate.

### Claim 11 (depends on 10)

The data driver as claimed in claim 10, wherein the first-second logic gate has a first input terminal and a second input terminal, the first input terminal of the first-second logic gate being coupled to the inversion output terminal of the first one of the logic units, the second input terminal of the first-second logic gate being coupled to an inversion output terminal of the fourth one of the logic units, the first-second logic gate having an output terminal that is coupled to the first-first switch, the first-second logic gate including an AND gate.

### Claim 12 (depends on 11)

The data driver as claimed in claim 11, wherein the first one of the logic units stores a least significant bit of the data.

### Claim 13 (depends on 11)

The data driver as claimed in claim 11, wherein the holding latch comprises a third-first switch coupled between an input terminal of a fourth one of the logic units and a power source, the third-first switch being turned on if the control signal includes a first polarity.

### Claim 14 (depends on 11)

The data driver as claimed in claim 11, wherein the second-second logic gate has a first input terminal and a second input terminal, the first input terminal of the second-second logic gate being coupled to the inversion output terminal of the second one of the logic units, the second input terminal of the second-second logic gate being coupled to the input terminal of a second one of the logic units, the second-second logic gate having an output terminal that is coupled to the second-first switch, the second-second logic gate including an AND gate.

### Claim 15 (depends on 10)

The data driver as claimed in claim 10, wherein each of the first-third logic gate and the second-third logic gate includes a NOR gate.

### Claim 16 (depends on 10)

The data driver as claimed in claim 10, wherein the fourth logic gate includes a NAND gate.

### Claim 17 (depends on 16)

The data driver as claimed in claim 16, wherein the fourth logic gate generates the counting signal if the control signal includes the first polarity.

### Claim 18 (depends on 10)

The data driver as claimed in claim 10, wherein the holding latch comprises:
a fifth logic gate for receiving an output from an output terminal of the fourth logic gate and for receiving a clock signal, the fifth logic gate including an AND gate; and
a second demultiplexer for receiving an output from a power source and an output of the fifth logic gate, the second demultiplexer receiving a start signal, the second demultiplexer outputting the output from the power source or the output of the fifth logic gate to the flip-flop unit included in the first one of the logic units depending on the start signal.

### Claim 19 (depends on 18)

The data driver as claimed in claim 18, wherein the start signal is supplied to the second demultiplexer during a time period in which the second switch is being turned on, the second demultiplexer outputting the output from the power source while the start signal is supplied, the second demultiplexer outputting the output of the fifth logic gate if the start signal is not supplied.

### Claim 20 (depends on 1)

The data driver as claimed in claim 1, wherein the digital-analog converter includes a transistor, a ramp pulse being supplied to a first terminal of the transistor and the counting signal being supplied to a gate of the transistor, the transistor being turned on while the counting signal is supplied making the ramp pulse output through a second terminal of the transistor.

### Claim 21 (depends on 1)

The data driver as claimed in claim 1, further comprising:
a shift register unit for sequentially generating a sampling signal;
a sampling latch unit for sequentially storing data corresponding to the sampling signal, and for providing the stored data to the holing latch unit; and
a buffer coupled to the data signal generator.

### Claim 22

A flat panel display comprising:
a pixel unit for displaying an image;
a scan driver for supplying a scan signal to the pixel unit;
a data driver for supplying a data signal to the pixel unit, the data driver comprising:
a holding latch for receiving data for the data driver and for receiving a control signal, the holding latch storing the data and outputting a counting signal that is generated according to the value of the data; and
a digital-analog converter for receiving a ramp pulse and the counting signal, the digital-analog converter determining a voltage level of the data signal by cropping the ramp pulse during a period for which the counting signal is supplied.

### Claim 23 (depends on 22)

The flat panel display as claimed in claim 22, wherein the holing latch includes a plurality of logic units, each of the logic units receiving, through an input terminal, a bit value the data, each of the logic units having an output terminal and an inversion output terminal, each of the logic units comprises:
a flip-flop unit;
a first logic gate, a first input terminal of the first logic gate being coupled to an output terminal of the flip-flop unit, a second input terminal of the first logic gate being coupled to the input terminal of the each of the logic units; and
a first demultiplexer being coupled to an output terminal of the first logic gate and the input terminal of the each of the logic units, the first demultiplexer outputting an output from the first logic gate or an output from the input terminal of the each of the logic units depending on a polarity of the control signal, an output terminal of the first demultiplexer being coupled to the flip-flop unit.