# US 2008/0186291 A1 · Display device

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- Number: US 2008/0186291 A1
- Document ID: US20080186291A1
- Status: Published application
- Kind: A1
- Application number: 11/902,740
- Filed: 2007-09-25
- Published: 2008-08-07
- Earliest claimed: 2006-10-03
- Assignees: Hitachi Displays, Ltd.
- Inventors: Katsumi Matsumoto; Kozo Yasuda; Hiroshi Kageyama
- Web page: https://patentgrep.com/patent/US20080186291A1

## CPC

- G09G 3/3688: {suitable for active matrices only}
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

The present invention is to prevent a capture error of display data caused by a delay due to a built-in driving circuit in a display device with a built-in driving circuit. The display device comprises: a display area having a plurality of sub pixels; and a driving circuit formed at the periphery of the display area; wherein the driving circuit includes: a first scanning circuit that performs scanning in a first direction; and a latch circuit which latches display data inputted from external based on a scanning output outputted from the first scanning circuit; wherein the driving circuit includes a timing correction circuit which corrects the timing of level change of the scanning output outputted from the first scanning circuit based on a display data synchronization clock inputted from external; wherein the latch circuit latches display data by means of a corrected scanning output outputted from the timing correction circuit; and wherein a transmission line up to the latch circuit of the display data and a transmission line up to the timing correction circuit of the display data synchronization clock are adjacently arranged.

## Claims

### Claim 1

A display device comprising:
a display area having a plurality of sub pixels; and
a driving circuit formed at the periphery of the display area;
wherein the driving circuit includes:
a first scanning circuit which performs scanning in a first direction; and
a latch circuit which latches display data inputted from external based on a scanning output outputted from the first scanning circuit;
wherein the driving circuit includes a timing correction circuit which corrects a timing of level change of the scanning output outputted from the first scanning circuit based on a display data synchronization clock inputted from external;
wherein the latch circuit latches display data by means of a corrected scanning output outputted from the timing correction circuit; and
wherein a transmission line up to the latch circuit of the display data and a transmission line up to the timing correction circuit of the display data synchronization clock are adjacently arranged.

### Claim 2 (depends on 1)

The display device according to the claim 1, wherein:
the same number of a plurality of inverter circuits are inserted in both the transmission line up to the latch circuit of the display data and the transmission line up to the timing correction circuit of the display data synchronization clock.

### Claim 3 (depends on 1)

The display device according to the claim 1, wherein:
the driving circuit includes a first driving pulse generation circuit which outputs a driving pulse for the first scanning circuit based on a horizontal synchronization signal and the display data synchronization clock inputted from external.

### Claim 4 (depends on 1)

The display device according to the claim 1, wherein:
the driving circuit is integrally formed with the display area by use of thin-film transistors on a substrate on which the display area is formed.

### Claim 5 (depends on 4)

The display device according to the claim 4, wherein:
each of the thin-film transistors includes a semiconductor layer of poly-silicon.

### Claim 6 (depends on 1)

The display device according to the claim 1, wherein:
the timing correction circuit is composed of:
a first clocked inverter which inputs the scanning output outputted from the first scanning circuit, the display data synchronization clock being applied to a clock terminal of the first clocked inverter; and
a second clocked inverter which inputs an output of the first clocked inverter, an inverted clock of the display data synchronization clock being applied to a clock terminal of the second clocked inverter.

### Claim 7 (depends on 1)

The display device according to the claim 1, wherein:
the driving circuit includes a second scanning circuit which performs scanning in a second direction different from the first direction.

### Claim 8 (depends on 7)

The display device according to the claim 7, comprising:
a second driving pulse generation circuit which outputs a driving pulse for the second scanning circuit based on the horizontal synchronization signal and a vertical synchronization signal inputted from external.