# US 2008/0186098 A1 · Circuit to prevent load-induced dc nonlinearity in an op-amp

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- Number: US 2008/0186098 A1
- Document ID: US20080186098A1
- Status: Published application
- Kind: A1
- Application number: 11/671,103
- Filed: 2007-02-05
- Published: 2008-08-07
- Earliest claimed: 2007-02-05
- Assignees: Analog Devices, Inc.
- Inventors: Moshe Gerstenhaber; Padraig Cooney
- Web page: https://patentgrep.com/patent/US20080186098A1

## CPC

- H03F 1/3211: {in differential amplifiers}
- H03F 3/4508: {using bipolar transistors as the active amplifying circuit (H03F3/45278 takes precedence)}
- H03F 3/45618: {by using balancing means}
- H03F 2203/45038: One or more current sources are added or changed as balancing means to reduce the offset of the dif amp
- H03F 2203/45212: the differential amplifier being designed to have a reduced offset
- H03F 2203/45538: the IC comprising balancing means, e.g. trimming means
- H03F 2203/45624: the LC comprising balancing means, e.g. trimming means
- H03F: AMPLIFIERS

## Abstract

A circuit for removing non-linearity produced when an amplifier includes a load that results in non-linear current levels is provided. The circuit includes a first transistor element being coupled to one of the differential inputs associated with the amplifier. A second transistor element is coupled to another of the differential inputs associated with the amplifier. The second transistor element is coupled to the current associated with the load. Current passing the collectors of the first and second transistors elements are arranged to be always equal so as to eliminate in the circuit the changes between the base currents of the second transistor element and first transistor element caused by the current associated with the load.

## Claims

### Claim 1

A circuit for removing non-linearity produced when an amplifier includes a load that results in non-linear current levels comprising:
a first transistor element being coupled to one of the differential inputs associated with said amplifier; and
a second transistor element being coupled to another of the differential inputs associated with said amplifier, said second transistor element being coupled to the current associated with said load;
wherein current passing the collectors of said first and second transistors elements are arranged to be always equal so as to eliminate in said circuit the changes between the base currents of said second transistor element and first transistor elements.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein said first transistor element comprises a bipolar transistor.

### Claim 3 (depends on 1)

The circuit of claim 1, wherein said second transistor element comprises a bipolar transistor.

### Claim 4 (depends on 3)

The circuit diagram of claim 3, wherein the emitter of said second transistor element is coupled to the current associated with said load.

### Claim 5 (depends on 3)

The circuit of claim 3, wherein the base of said first transistor element is coupled to said one of the differential inputs.

### Claim 6 (depends on 3)

The circuit of claim 3, wherein the base of said second transistor element is coupled to said another of the differential inputs.

### Claim 7 (depends on 3)

The circuit of claim 3, wherein the collector of said second transistor element is coupled to a first current source.

### Claim 8 (depends on 3)

The circuit of claim 3, wherein the emitter of said second transistor element is coupled to a second current source.

### Claim 9 (depends on 3)

The circuit of claim 3, wherein the emitter of said first transistor element is coupled to a third current source.

### Claim 10

A method of removing non-linearity produced when an amplifier includes a load that results in non-linear current levels comprising:
coupling a first transistor element coupled to one of the differential inputs associated with said amplifier; and
coupling a second transistor element to another of the differential inputs associated with said amplifier, said second transistor element being coupled to the current associated with said load;
arranging said first and second transistor elements so that current passing the collectors of said first and second transistors elements are always equal so as to eliminate in said circuit the changes between the base currents of said second transistor element and first transistor element caused by the current associated with said load.

### Claim 11 (depends on 10)

The method of claim 10, wherein said first transistor element comprises a bipolar transistor.

### Claim 12 (depends on 10)

The method of claim 10, wherein said second transistor element comprises a bipolar transistor.

### Claim 13 (depends on 12)

The method diagram of claim 12, wherein the emitter of said second transistor element is coupled to the current associated with said load.

### Claim 14 (depends on 12)

The method of claim 12, wherein the base of said first transistor element is coupled to said one of the differential inputs.

### Claim 15 (depends on 12)

The method of claim 12, wherein the base of said second transistor element is coupled to said another of the differential inputs.

### Claim 16 (depends on 12)

The method of claim 12, wherein the collector of said second transistor element is coupled to a first current source.

### Claim 17 (depends on 12)

The method of claim 12, wherein the emitter of said second transistor element is coupled to a second current source.

### Claim 18 (depends on 12)

The method of claim 12, wherein the emitter of said first transistor element is coupled to a third current source.