# US 2008/0186069 A1 · Design structure for dynamic latch state saving device and protocol > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2008/0186069 A1 - Document ID: US20080186069A1 - Status: Published application - Kind: A1 - Application number: 12/099,423 - Filed: 2008-04-08 - Published: 2008-08-07 - Earliest claimed: 2006-09-12 - Assignees: International Business Machines Corporation - Inventors: Pascal A. Nsame; Anthony J. Perri; Lansing D. Pickup; Sebastian T. Ventrone; Matthew R. Welland - Web page: https://patentgrep.com/patent/US20080186069A1 ## CPC - G11C 5/145: {Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence)} - H03K 3/356008: {ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00)} - G11C: STATIC STORES (semiconductor memory devices H10B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract The invention comprises a design structure for a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated to said charge device, a data signal output distributed from the charge device, and a clock signal allotted to the charge device, wherein said integrated recovery mechanism maintains a state of the charge device independent of the charge device. ## Claims ### Claim 1 A design structure embodied in a machine readable medium, the design structure comprising a dynamic state-saving latch electrical circuit comprising: a charge device; an integrated recovery mechanism; and a single supply voltage rail connected to said charge device and said integrated recovery mechanism, wherein when said supply voltage rail is active, said charge device maintains a state of said charge device and wherein when said supply voltage rail is inactive, said integrated recovery mechanism maintains a state of said charge device. ### Claim 2 (depends on 1) The design structure of claim 1, all the limitations of which are incorporated herein by reference, wherein said integrated recovery mechanism holds said state independently of said charge device. ### Claim 3 (depends on 1) The design structure of claim 1, all the limitations of which are incorporated herein by reference, further comprising a hold signal generator connected to said integrated recovery mechanism, wherein when said supply voltage rail is inactive, said hold signal generator is adapted to generate a hold signal and to provide said hold signal to said integrated recovery mechanism. ### Claim 4 (depends on 3) The design structure of claim 3, all the limitations of which are incorporated herein by reference, wherein said hold signal uses less power than said voltage rail. ### Claim 5 (depends on 3) The design structure of claim 3, all the limitations of which are incorporated herein by reference, wherein said hold signal generator provides said hold signal from one of: a voltage domain that does not comprise said latch and is active; and an external source not on said voltage domain. ### Claim 6 (depends on 1) The design structure of claim 1, all the limitations of which are incorporated herein by reference, wherein the design structure comprises a netlist. ### Claim 7 (depends on 1) The design structure of claim 1, all the limitations of which are incorporated herein by reference, wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits. ### Claim 8 (depends on 1) The design structure of claim 1, all the limitations of which are incorporated herein by reference, all the limitations of which are incorporated herein by reference, wherein the design structure resides in a programmable gate array. ### Claim 9 A design structure embodied in a machine readable medium, the design structure comprising a dynamic state-saving latch electrical circuit comprising: a charge device; an integrated recovery mechanism, wherein said integrated recovery mechanism and said charge device are on a first voltage domain; a single supply voltage rail connected to said charge device and said integrated recovery mechanism; and a hold signal generator connected to said integrated recovery mechanism, wherein when said supply voltage rail is active, said charge device maintains a state of said charge device and wherein when said supply voltage rail is inactive, said hold signal generator is adapted to control said integrated recovery mechanism to maintain a state of said charge device. ### Claim 10 (depends on 9) The design structure of claim 9, all the limitations of which are incorporated herein by reference, wherein said hold signal is provided from a second voltage domain that does not comprise said latch and is active or wherein said hold signal is provided from an external source not on one of said first voltage domain and said second voltage domain. ### Claim 11 (depends on 9) The design structure of claim 9, all the limitations of which are incorporated herein by reference, wherein when said supply voltage rail is inactive, said hold signal generator is adapted to generate said hold signal. ### Claim 12 (depends on 9) The design structure of claim 9, all the limitations of which are incorporated herein by reference, wherein said hold signal uses less power than said voltage rail. ### Claim 13 (depends on 9) The design structure of claim 9, all the limitations of which are incorporated herein by reference, wherein said integrated recovery mechanism is adapted to maintain said state without the need for additional voltage rails. ### Claim 14 (depends on 9) The design structure of claim 9, all the limitations of which are incorporated herein by reference, wherein the design structure comprises a netlist. ### Claim 15 (depends on 9) The design structure of claim 9, all the limitations of which are incorporated herein by reference, wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits. ### Claim 16 (depends on 9) The design structure of claim 9, all the limitations of which are incorporated herein by reference, wherein the design structure resides in a programmable gate array.