# US 2008/0186068 A1 · Circuit and technique for adjusting and accurately controlling clock duty cycles in integrated circuit devices

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- Number: US 2008/0186068 A1
- Document ID: US20080186068A1
- Status: Published application
- Kind: A1
- Application number: 11/671,383
- Filed: 2007-02-05
- Published: 2008-08-07
- Earliest claimed: 2007-02-05
- Assignees: ProMOS Technologies PTE.LTD.
- Inventors: John D. Heightley
- Web page: https://patentgrep.com/patent/US20080186068A1

## CPC

- H03K 5/1565: {the output pulses having a constant duty cycle}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A circuit and technique for adjusting and accurately controlling clock duty cycles in integrated circuit devices in which only N-channel current regulating transistors are used in the voltage-controlled inverters and both the rising and falling edges can be adjusted by cascading two such inverters. The potential for cascading of these inverters allows for additional accuracy to be achieved.

## Claims

### Claim 1

A duty cycle adjusting circuit comprising:
first and second cascaded voltage-controlled inverters coupled between a supply voltage source and a reference voltage level, said first voltage-controlled inverter receiving a first control voltage at an input thereof and said second voltage-controlled inverter receiving a second control voltage at an input thereof, said first and second control voltages moving in opposite directions as an output of said circuit diverges from a 50% duty cycle.

### Claim 2 (depends on 1)

The circuit of claim 1 wherein as said output of said circuit is greater than a 50% duty cycle, said first control voltage decreases and said second control voltage increases.

### Claim 3 (depends on 1)

The circuit of claim 1 wherein as said output of said circuit is less than a 50% duty cycle, said first control voltage increases and said second control voltage decreases.

### Claim 4 (depends on 1)

The circuit of claim 1 further comprising third and fourth voltage-controlled inverters coupled in cascade with said first and second cascaded voltage-controlled inverters, odd numbered ones of said voltage-controlled inverters receiving said first control voltage and even numbered ones of said voltage-controlled inverters receiving said second control voltage.

### Claim 5 (depends on 4)

The circuit of claim 4 further comprising a plurality of voltage-controlled inverters coupled in cascade with said first and second cascaded voltage-controlled inverters, odd numbered ones of said plurality of voltage-controlled inverters receiving said first control voltage and even numbered ones of said plurality of voltage-controlled inverters receiving said second control voltage.

### Claim 6 (depends on 1)

The circuit of claim 1 wherein said first and second control voltages are initialized to substantially one half of said supply voltage.

### Claim 7 (depends on 1)

The circuit of claim 1 wherein each of said first and second voltage-controlled inverters comprise an N-channel current controlled transistor.

### Claim 8 (depends on 7)

The circuit of claim 7 wherein each of said first and second voltage-controlled inverters further comprise series coupled P-channel and N-channel transistors in series with said N-channel current controlled transistor coupled between said supply voltage source and said reference voltage level.

### Claim 9 (depends on 1)

The circuit of claim 1 wherein a switching point of each of said first and second voltage-controlled inverters is controlled by said respective first and second control voltages.

### Claim 10 (depends on 1)

The circuit of claim 1 wherein said first and second control voltages are each generated by a single bi-directional current path in a dual slope integrator voltage generator.

### Claim 11

A duty cycle adjuster circuit comprising:
a first voltage-controlled inverter receiving an input clock signal and a first control voltage; and
a second voltage-controlled inverter coupled to an output of said first voltage-controlled inverter and receiving a second control voltage, said second voltage-controlled inverter providing a corrected output clock signal in response to said output of said first voltage-controlled inverter and said second control voltage.

### Claim 12 (depends on 11)

The circuit of claim 11 wherein said first and second control voltages move in opposite directions as said corrected output clock signal diverges from a 50% duty cycle.

### Claim 13 (depends on 11)

The circuit of claim 11 wherein as said corrected output clock signal exhibits a duty cycle greater than 50%, said first control voltage decreases and said second control voltage increases.

### Claim 14 (depends on 11)

The circuit of claim 11 wherein as said corrected output clock signal exhibits a duty cycle lass than 50%, said first control voltage increases and said second control voltage decreases.

### Claim 15 (depends on 11)

The circuit of claim 11 further comprising third and fourth voltage-controlled inverters coupled in cascade with said first and second voltage-controlled inverters, odd numbered ones of said voltage-controlled inverters receiving said first control voltage and even numbered ones of said voltage-controlled inverters receiving said second control voltage.

### Claim 16 (depends on 15)

The circuit of claim 15 further comprising a plurality of voltage-controlled inverters coupled in cascade with said first and second voltage-controlled inverters, odd numbered ones of said plurality of voltage-controlled inverters receiving said first control voltage and even numbered ones of said plurality of voltage-controlled inverters receiving said second cascaded control voltage.

### Claim 17 (depends on 11)

The circuit of claim 11 wherein said first and second control voltages are initialized to substantially one half of a supply voltage.

### Claim 18 (depends on 11)

The circuit of claim 11 wherein each of said first and second voltage-controlled inverters comprise an N-channel current controlled transistor.

### Claim 19 (depends on 18)

The circuit of claim 18 wherein each of said first and second cascaded voltage-controlled inverters further comprise series coupled P-channel and N-channel transistors in series with said N-channel current controlled transistor.

### Claim 20 (depends on 11)

The circuit of claim 11 wherein a switching point of each of said first and second voltage-controlled inverters is controlled by said respective first and second control voltages.

### Claim 21 (depends on 11)

The circuit of claim 11 wherein said first and second control voltages are each generated by a single bi-directional current path in a dual slope integrator voltage generator.

### Claim 22

A method for adjusting the duty cycle of an input signal comprising:
providing first and second series coupled inverters;
firstly adjusting a propagation delay of a rising edge of said input signal with said first inverter; and
secondly adjusting a propagation delay of a falling edge of said input signal with said second inverter.

### Claim 23 (depends on 22)

The method of claim 22 wherein said act of firstly adjusting said propagation delay of said rising edge of said input signal comprises:
adjusting a slew rate of a falling edge of an output of said first inverter.

### Claim 24 (depends on 22)

The method of claim 22 wherein said act of secondly adjusting a propagation delay of a falling edge of said input signal comprises:
adjusting a slew rate of a falling edge of an output of said second inverter.

### Claim 25 (depends on 22)

The method of claim 22 further comprising:
supplying respective first and second control signals to said first and second inverters; and
adjusting a switching threshold of said first and second inverters in response to said control signals.

### Claim 26 (depends on 25)

The method of claim 25 further comprising:
reducing said first control signal to reduce said falling edge slew rate of said first inverter and increase a propagation delay of a rising edge of said input signal.

### Claim 27 (depends on 26)

The method of claim 26 wherein said act of reducing said first control signal further comprises:
further reducing said first control signal to increase said switching threshold of said first inverter and further increase a propagation delay of said rising edge of said input signal.

### Claim 28 (depends on 25)

The method of claim 25 further comprising:
increasing said first control signal to increase said falling edge slew rate of said first inverter and reduce a propagation delay of a rising edge of said input signal.

### Claim 29 (depends on 28)

The method of claim 28 wherein said act of increasing said first control signal further comprises:
further increasing said first control signal to decrease said switching threshold of said first inverter and further decrease a propagation delay of said rising edge of said input signal.

### Claim 30 (depends on 25)

The method of claim 25 further comprising:
reducing said second control signal to reduce said falling edge slew rate of said second inverter and increase a propagation delay of a falling edge of said input signal.

### Claim 31 (depends on 30)

The method of claim 30 wherein said act of reducing said second control signal further comprises:
further reducing said second control signal to increase said switching threshold of said second inverter and further increase a propagation delay of said falling edge of said input signal.

### Claim 32 (depends on 25)

The method of claim 25 further comprising:
increasing said second control signal to increase said falling edge slew rate of said second inverter and reduce a propagation delay of a falling edge of said input signal.

### Claim 33 (depends on 32)

The method of claim 32 wherein said act of increasing said second control signal further comprises:
further increasing said second control signal to decrease said switching threshold of said second inverter and further decrease a propagation delay of said falling edge of said input signal.

### Claim 34

A duty cycle adjusting circuit having compensation for self-generated duty cycle error comprising:
cascade coupled first and second voltage-controlled inverters for coupling between a supply voltage and a reference voltage;
cascade coupled third and fourth voltage-controlled inverters for coupling between said supply voltage and said reference voltage;
a first non-voltage-controlled inverter cascaded between an output of said second voltage-controlled inverter and an input of said third voltage-controlled inverter;
a second non-voltage-controlled inverter cascaded between an output of said fourth voltage-controlled inverter and an output of said circuit;
said first and fourth voltage-controlled inverters receiving a first control voltage at control inputs thereof and said second and third voltage-controlled inverters receiving a second control voltage a control inputs thereof, said first and second control voltages moving in opposite directions thereof as said output of said circuit diverges from a 50% duty cycle.