# US 2008/0186062 A1 · Frequency Divider

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- Number: US 2008/0186062 A1
- Document ID: US20080186062A1
- Status: Published application
- Kind: A1
- Application number: 11/573,349
- Filed: 2005-07-27
- Published: 2008-08-07
- Earliest claimed: 2004-08-06
- Assignees: Koninklijke Philips Electronics N.V.
- Inventors: Prashant Dekate; Dominicus Martinus Wilhelmus Leenaerts
- Web page: https://patentgrep.com/patent/US20080186062A1

## CPC

- H03K 23/505: {with a base which is an odd number}
- H03K 23/662: {by adding or suppressing pulses}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A frequency divider providing an odd integer division factor comprising a binary counter (10) providing an even integer division factor, which is the first even number smaller than the odd division factor, the binary counter having a clock input for receiving a periodical clock signal (Ck) having a frequency. The circuit further comprises an end of count circuit (20) coupled to the binary counter and generating an End Of Count signal (EOC) for a clock (Ck) period after every even integer number periods of the clock signal (Ck), the end of count signal (EOC) being inputted to an input (IN) of the counter (10). The circuit further includes an output generator (30) coupled to the binary counter and to the clock signal (Ck), the output generator (30) generating an output signal (OUT) having a frequency which is substantially equal with the frequency of the frequency signal (Ck) divided by the odd division factor

## Claims

### Claim 1

A frequency divider providing an odd integer division factor comprising:
a binary counter for providing an even integer division factor, which is the odd division factor minus one, the binary counter having a clock input for receiving a periodical clock signal having a frequency,
an end of count circuit coupled to the binary counter for generating,
an End Of Count signal for a clock period after every said even integer number periods of the clock signal the end of count signal being inputted to an input of the counter, and
an output generator coupled to the binary counter and to the clock frequency that is substantially equal to the frequency of the frequency signal divided by the odd division factor.

### Claim 2 (depends on 1)

A frequency divider as claimed in claim 1, wherein the output generator is a combinatorial logic circuit.

### Claim 3 (depends on 1)

A frequency divider circuit as claimed in claim 1, wherein the end of count circuit comprises an AND gate for receiving two most significant bits generated by the binary counter and for providing a signal for changing a state of a flip-flop for a clock period.

### Claim 4 (depends on 3)

A frequency divider circuit as claimed as claimed in claim 3, wherein the flip-flop is a D flip-flop.

### Claim 5 (depends on 1)

A frequency divider as claimed in claim 1, wherein the binary counter is a Gray counter.

### Claim 6 (depends on 1)

A frequency divider circuit as claimed as claimed in claim 1, wherein the binary counter comprises D flip-flops.

### Claim 7 (depends on 5)

A frequency divider as claimed in claim 5, wherein the output signal generated by the output generator has substantially 50% duty cycle.