# US 2008/0186035 A1 · On chip temperature measuring and monitoring method

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- Number: US 2008/0186035 A1
- Document ID: US20080186035A1
- Status: Published application
- Kind: A1
- Application number: 12/061,692
- Filed: 2008-04-03
- Published: 2008-08-07
- Earliest claimed: 2004-04-14
- Assignees: International Business Machines Corperation
- Inventors: Robert L. Franch; Keith A. Jenkins
- Web page: https://patentgrep.com/patent/US20080186035A1

## CPC

- H10D 89/601: {for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs}
- G01K 7/01: using semiconducting elements having PN junctions (G01K7/02, G01K7/16, G01K7/30 take precedence)
- G01K 7/015: {using microstructures, e.g. made of silicon}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G01K: MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR (radiation pyrometry G01J5/00)

## Abstract

A device temperature measurement circuit, an integrated circuit (IC) including a device temperature measurement circuit, a method of characterizing device temperature and a method of monitoring temperature. The circuit includes a constant current source and a clamping device. The clamping device selectively shunts current from the constant current source or allows the current to flow through a PN junction, which may be the body to source/drain junction of a field effect transistor (FET). Voltage measurements are taken directly from the PN junction. Junction temperature is determined from measured junction voltage.

## Claims

### Claim at position 1

1-19. (canceled)

### Claim 20

A method of modeling a field effect transistor (FET) in a circuit on an integrated circuit (IC) chip, said FET being modeled for varying temperature, said method comprising the steps of:
a) determining a voltage to temperature relationship for a PN junction at a known current, said PN junction being a body to source/drain junction of a FET;
b) operating said FET normally; and
c) measuring voltage across said PN junction, measured said voltage indicating the instantaneous temperature of said PN junction, a device temperature model being derived from indicated said instantaneous temperature.

### Claim 21 (depends on 20)

A method of modeling said FET as in claim 20, wherein the step (a) of determining said voltage to temperature relationship for the PN junction comprises the steps of:
i) ramping temperature on said PN junction;
ii) providing said known current to said PN junction from an on-chip current source; and
iii) measuring voltage across said PN junction until a maximum selected temperature is reached.

### Claim 22 (depends on 21)

A method of modeling said FET as in claim 21, wherein said voltage is periodically measured in step (iii).

### Claim 23 (depends on 20)

A method of modeling said FET as in claim 20, wherein the step (b) of operating the FET normally comprises reducing current provided from an on-chip current source to said PN junction.

### Claim 24 (depends on 23)

A method of modeling said FET as in claim 23, wherein said on-chip current source is a constant current source and reducing current comprises shunting said constant current source, whereby voltage across said PN junction is below a turn on point for said PN junction.

### Claim 25 (depends on 20)

A method of modeling said FET as in claim 20, wherein the measuring step (c) comprises halting operation of said FET.

### Claim 26 (depends on 25)

A method of modeling said FET as in claim 25, wherein said FET is included in an inverter in a ring oscillator including said inverter and, halting operation of said FET comprises stopping oscillation of said ring oscillator.

### Claim 27 (depends on 26)

A method of modeling said FET as in claim 26, wherein stopping said ring oscillator further comprises turning off a shunt shunting current from an on chip current source, said current flowing through said PN junction.

### Claim 28 (depends on 27)

A method of modeling said FET as in claim 27, wherein the measuring step (c) further comprises periodically measuring said voltage across said PN junction.

### Claim at position 11

29-31. (canceled)