# US 2008/0185735 A1 · Dynamic pad size to reduce solder fatigue

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- Number: US 2008/0185735 A1
- Document ID: US20080185735A1
- Status: Published application
- Kind: A1
- Application number: 11/701,651
- Filed: 2007-02-02
- Published: 2008-08-07
- Earliest claimed: 2007-02-02
- Assignees: Freescale Semiconductor, Inc.
- Inventors: Tim V. Pham; Trent S. Uehling
- Web page: https://patentgrep.com/patent/US20080185735A1

## CPC

- H05K 1/111: {Pads for surface mounting, e.g. lay-out}
- H10W 70/65: Shapes or dispositions of interconnections
- H05K 3/3436: {having an array of bottom contacts, e.g. pad grid array or ball grid array components}
- H05K 2201/09418: Special orientation of pads, lands or terminals of component, e.g. radial or polygonal orientation
- H05K 2201/10734: Ball grid array [BGA]; Bump grid array
- H10W 72/07251: {characterised by changes in properties of the bump connectors during connecting}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/90: Bond pads, in general
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- Y02P 70/50: Manufacturing or production processes characterised by the final manufactured product
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS

## Abstract

A semiconductor device is provided which comprises a substrate (501) having a plurality of bond pads (503) disposed thereon. Each bond pad has a major axis and a minor axis in a direction parallel to the substrate, and the ratio of the major axis to the minor axis increases with the distance of a bond pad from the center of the substrate.

## Claims

### Claim 1

A method for making a semiconductor device, comprising:
providing a substrate; and
creating a plurality of bond pads on said substrate, wherein each bond pad has a major axis and a minor axis in a plane parallel to the substrate, and wherein the ratio of the major axis to the minor axis increases with the distance of a bond pad from the center of the substrate.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming a solder joint on each of said plurality of bond pads.

### Claim 3 (depends on 2)

The method of claim 2, wherein the major axis of each bond pad is essentially parallel to the major axis of thermal expansion of the solder joint in a direction parallel to the substrate.

### Claim 4 (depends on 2)

The method of claim 2, wherein the substrate has a layer of solder resist disposed thereon, and wherein the plurality of bond pads is formed by a process that includes selectively removing portions of the solder resist.

### Claim 5 (depends on 2)

The method of claim 2, wherein the substrate is a packaging substrate, and wherein each solder joint is attached on a first end to one of said plurality of bond pads, and is attached on a second end to a semiconductor die.

### Claim 6 (depends on 2)

The method of claim 2, wherein the dimension of the bond pad in any direction in the plane is proportional to the relative strain experienced by the solder joint in that direction.

### Claim 7 (depends on 1)

The method of claim 1, wherein the ratio of the major axis to the minor axis of each of said plurality of bond pads is essentially proportional to the distance of the bond pad from the center of the substrate.

### Claim 8 (depends on 7)

The method of claim 7, wherein the substrate has a die disposed thereon, and wherein the ratio ds of the major axis to the minor axis of any of said plurality of bond pads is essentially given by the equation
ds=ΔCTE*L
where L is the distance from the center of the substrate, and wherein ΔCTE is the CTE stress differential between the die and the substrate.

### Claim 9 (depends on 8)

The method of claim 8, where ΔCTE is given by the equation
ΔCTE=ΔT*(CTEsubstrate−CTEdie)
wherein
ΔT is the temperature range to which the device is exposed;
CTEsubstrate is the coefficient of thermal expansion of the substrate; and
ΔCTEdie is the coefficient of thermal expansion of the die.

### Claim 10 (depends on 1)

The method of claim 1, wherein each of said plurality of bond pads is essentially elliptical in shape in a cross-section taken along a plane parallel to the substrate.

### Claim 11

A semiconductor device, comprising:
a substrate having a plurality of bond pads disposed thereon;
wherein each bond pad has a major axis and a minor axis in a direction parallel to the substrate, and wherein the ratio of the major axis to the minor axis increases with the distance of a bond pad from the center of the substrate.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the ratio of the major axis to the minor axis of each of said plurality of bond pads is essentially proportional to the distance of the bond pad from the center of the substrate.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, further comprising a die disposed on said substrate, and where the ratio ds of the major axis to the minor axis of any of said plurality of bond pads is essentially given by the equation
ds=ΔCTE*L
wherein L is the distance from the center of the substrate, and wherein ΔCTE is the CTE stress differential between the die and the substrate.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, where ΔCTE is given by the equation
ΔCTE=ΔT*(CTEsubstrate−CTEdie)
wherein
ΔT is the temperature range to which the device is exposed;
CTEsubstrate is the coefficient of thermal expansion of the substrate; and
ΔCTEdie is the coefficient of thermal expansion of the die.

### Claim 15 (depends on 11)

The semiconductor device of claim 11, wherein each of said plurality of bond pads is essentially elliptical in shape.

### Claim 16 (depends on 11)

The semiconductor device of claim 11, wherein the semiconductor device is a flip-chip device.

### Claim 17

A method for making a semiconductor device, comprising:
providing an initial data set relating to the dimensions and position of a bond pad on a semiconductor substrate;
determining an axis of expansion for the semiconductor substrate;
adjusting the dimensions of at least one of said bond pads as a function of the axis of expansion, thereby deriving an adjusted data set; and
using the adjusted data set to define a bond pad in a semiconductor device.

### Claim 18 (depends on 17)

The method of claim 17, wherein each of said plurality of bond pads is essentially elliptical in shape in a cross-section taken along a plane parallel to the substrate.

### Claim 19 (depends on 17)

The method of claim 17, wherein the cross-sectional areas of the plurality of bond pads along a plane parallel to the substrate are essentially equal.

### Claim 20 (depends on 17)

The method of claim 17, wherein the data set is a solder mask data set.