# US 2008/0185731 A1 · Stacked structure of semiconductor chips, memory card, and method of manufacturing stacked structure of semiconductor chips > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2008/0185731 A1 - Document ID: US20080185731A1 - Status: Published application - Kind: A1 - Application number: 12/022,234 - Filed: 2008-01-30 - Published: 2008-08-07 - Earliest claimed: 2007-02-01 - Assignees: Matsushita Electric Industrial Co., Ltd. - Inventors: Manabu Gokan; Akihisa Nakahashi; Koichi Nagai; Naoki Suzuki - Web page: https://patentgrep.com/patent/US20080185731A1 ## CPC - H10W 90/00: Package configurations - G11C 5/02: Disposition of storage elements, e.g. in the form of a matrix array - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 74/131: {the semiconductor body being only partially enclosed} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/01515: {Forming coatings} - H10W 72/075: {of bond wires} - H10W 72/251: {Materials} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/536: {the connected ends being ball-shaped} - H10W 72/5363: {the connected ends being wedge-shaped} - H10W 72/5522: {comprising gold [Au]} - H10W 72/865: {Die-attach connectors and bond wires} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 90/20: Configurations of stacked chips - H10W 90/231: {the stacked chips being on both top and bottom sides of an auxiliary carrier having no electrical connection structure} - H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape - H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips} - H10W 90/721: {of bump connectors} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A stacked structure of semiconductor chips includes plural stacked semiconductor chips and plural tabular holding members which hold the respective semiconductor chips. At least two holding members among the holding members are arranged in places at ends of the semiconductor chips where inner side facets of the holding members are opposed to each other, at least one semiconductor chip of the two semiconductor chips held by the two holding members, respectively, is held by only one holding member of the holding members at one end of the semiconductor chip, and all or a part of the one semiconductor chip is arranged in the largest space positioned in an inner side of the inner side facet of the other holding member of the holding members, the largest space being formed by a surface including the one surface of the other holding member, a surface including the other surface of the other holding member, and a surface including a surface of the other semiconductor chip held by the other holding member, the other semiconductor chip being closer to the other holding member. ## Claims ### Claim 1 A stacked structure of semiconductor chips comprising: plural stacked semiconductor chips; and plural tabular holding members which hold the respective semiconductor chips, wherein at least two holding members among the holding members are arranged in places at ends of the semiconductor chips where inner side facets of the holding members are opposed to each other, at least one semiconductor chip of the two semiconductor chips held by the two holding members, respectively, is held by only one holding member of the holding members at one end of the semiconductor chip, and all or a part of the one semiconductor chip is arranged in the largest space positioned in an inner side of the inner side facet of the other holding member of the holding members, the largest space being formed by a surface including the one surface of the other holding member, a surface including the other surface of the other holding member, and a surface including a surface of the other semiconductor chip held by the other holding member, the other semiconductor chip being closer to the other holding member. ### Claim 2 (depends on 1) The stacked structure of semiconductor chips according to claim 1, wherein the semiconductor chip is held on at least one surface of the one holding member. ### Claim 3 (depends on 2) The stacked structure of semiconductor chips according to claim 2, wherein the other semiconductor chip is adjacent to the one semiconductor chip and held by only the other holding member at the other end opposed to the one end, and the largest space is a space positioned in an inner side of the inner side facet of the other holding member and is formed by a surface including a surface on an opposite side of the other semiconductor chip side of the other holding member and a surface including a surface on the holding member side of the other semiconductor chip. ### Claim 4 (depends on 3) The stacked structure of semiconductor chips according to claim 3, wherein the plural stacked semiconductor chips have a plurality of the one semiconductor chips and a plurality of the other semiconductor chips both of which are alternately stacked, and all or a part of the other semiconductor chip is arranged in a space positioned in an inner side of the inner side facet of the one holding member, the space being formed by a surface including a surface on an opposite side of the one semiconductor chip side of the one holding member and a surface including a surface on the one holding member side of the one semiconductor chip. ### Claim 5 (depends on 1) The stacked structure of semiconductor chips according to claim 1, wherein the semiconductor chips are held on both surfaces of the other holding member, the largest space is a space positioned in an inner side of the inner side facet of the other holding member and is formed by a surface including a surface on the holding member side of the semiconductor chip held on one surface of the other holding member and a surface including a surface on the holding member side of the semiconductor chip held on the other surface of the other holding member, and arrangement of the entire one semiconductor ship or a part of the one semiconductor chip in the space means that the semiconductor chip held by the one holding member is arranged between the semiconductor chips arranged on both the surfaces of the other holding member. ### Claim 6 (depends on 5) The stacked structure of semiconductor chips according to claim 5, wherein the semiconductor chips are held on both surfaces of the one holding member, and one semiconductor chip of the semiconductor chips held on both the surfaces of the one holding member is arranged between the semiconductor chips arranged on both the surfaces of the other holding member. ### Claim 7 (depends on 6) The stacked structure of semiconductor chips according to claim 6, wherein one semiconductor chip of the semiconductor chips held on both surfaces of the one holding member by one holding member adjacent to the one holding member is further arranged between the semiconductor chips arranged on both the sides of the other holding member. ### Claim 8 (depends on 1) The stacked structure of semiconductor chips according to claim 1, wherein the holding members are substrates, and the semiconductor chips are mounted on the substrates by flip chip or wire bonding. ### Claim 9 (depends on 8) The stacked structure of semiconductor chips according to claim 8, wherein adjacent substrates of the substrates are electrically connected by a conductive member, and a space between the adjacent substrates is adjusted by the conductive member. ### Claim 10 (depends on 1) A memory card comprising: a mother board on which one or plural stacked modules having the stacked structure of semiconductor chips according to claim 1 are arranged; and an IC chip for controlling the semiconductor chips. ### Claim 11 A method of manufacturing a stacked structure of semiconductor chips including plural stacked semiconductor chips and plural tabular holding members which hold the respective semiconductor chips, the method comprising a stacking step of arranging the semiconductor chip held by the holding member at one end thereof such that at least a part of the semiconductor chip overlaps a space formed on inner sides of inner side facets of the holding members which hold the other semiconductor chips. ### Claim 12 A method of manufacturing a stacked structure of semiconductor chips including: plural stacked semiconductor chips; and plural tabular holding members which hold the respective semiconductor chips, in which at least two holding members among the holding members are arranged in places at ends of the semiconductor chips where inner side facets of the holding members are opposed to each other, and at least one semiconductor chip of the two semiconductor chips held by the two holding members, respectively, is held by only one holding member of the holding members at one end of the semiconductor chip, the method comprising a stacking step of arranging semiconductor chips so that all or a part of the one semiconductor chip is arranged in the largest space positioned in an inner side of the inner side facet of the other holding member of the holding members, the largest space being formed by a surface including the one surface of the other holding member, a surface including the other surface of the other holding member, and a surface including a surface of the other semiconductor chip held by the other holding member, the other semiconductor chip being closer to the other holding member. ### Claim 13 A stacked structure of semiconductor chips comprising: plural stacked semiconductor chips; and plural tabular holding members which hold the respective semiconductor chips, wherein at least two holding members among the holding members are arranged in places at ends of the semiconductor chips, at least one semiconductor chip of the two semiconductor chips held by the two holding members, respectively, is held by only one holding member of the holding members at one end of the semiconductor chip, and all or a part of the one semiconductor chip is arranged so as to be intersected the other semiconductor chip in the view of the direction of stacking, and arranged in the largest space positioned in an inner side of the inner side facet of the other holding member of the holding members, the largest space being formed by a surface including the one surface of the other holding member, a surface including the other surface of the other holding member, and a surface including a surface of the other semiconductor chip held by the other holding member, the other semiconductor chip being closer to the other holding member. ### Claim 14 A semiconductor device, comprising: a plurality of semiconductor chips; and a plurality of substrates to which said semiconductor chips are mounted to, respectively; one of said substrates on a left side of said device, one of said chips mounted thereto extending past a right edge of said one of said substrates; another of said substrates on a right side of said device, another said of chips mounted thereto extending past a left edge of said another of said substrates; said another of said chips partially over and laterally offset relative to said one of said chips.