# US 2008/0185720 A1 · Package structure and method for chip with two arrays of bonding pads on BGA substrate for preventing gold bonding wires from collapse

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- Number: US 2008/0185720 A1
- Document ID: US20080185720A1
- Status: Published application
- Kind: A1
- Application number: 12/007,361
- Filed: 2008-01-09
- Published: 2008-08-07
- Earliest claimed: 2007-02-02
- Assignees: Integrated Circuit Solution Inc.
- Inventors: Ming-Feng Wu
- Web page: https://patentgrep.com/patent/US20080185720A1

## CPC

- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 70/68: Shapes or dispositions thereof
- H10W 72/075: {of bond wires}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/50: Bond wires
- H10W 72/5366: {the bond wires having kinks}
- H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements}
- H10W 72/5473: {multiple bond wires connected to a common bond pad}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/581: {Auxiliary members, e.g. flow barriers}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A package structure and method for preventing gold bonding wires from collapsing are disclosed. The structure is especially useful for those chips whose two n×1 arrays of bonding pads are on the chip center to be packaged on a BGA substrate. According to the first preferred embodiment, two dies having a redistribution layer formed thereon are introduced outer the bonding pad array on the chip so that the gold bonding wires can be divided into two sections each to connect the bonding pads with the redistribution layer and the redistribution layer with the gold fingers on the BGA substrate. According to the second embodiment, the gold bonding wires are fixed by the epoxy strips on the chips after bonding the bonding pads to the gold fingers but before pouring liquid encapsulated epoxy into a mold.

## Claims

### Claim 1

A package structure for preventing gold bonding wires from collapsing, which is especially useful for those chips whose bonding pads are on the chip center to be packaged on a BGA substrate, the package structure comprising:
a BGA substrate;
a BGA chip whose bottom is connected to the BGA substrate by a insulating sealant, and the BGA chip having at least two arrays of boning pads;
two dummy dies connecting to the upper surface of the chip, the upper surface of the dummy dies having redistribution layers which corresponds to the bonding pads;
two first gold bonding wires respectively connecting from the bonding pads in the first and the second arrays to one end of redistribution layers of the two dummy dies, and the redistribution layers having the other end connecting to the gold fingers on the upper surface of the BGA substrate by two second gold bonding wires.

### Claim 2 (depends on 1)

The package structure of claim 1, wherein the dummy die is a silicon substrate on which is formed with a oxidizing layer and a metal layer.

### Claim 3 (depends on 1)

The package structure of claim 1, wherein the insulating sealant is epoxy.

### Claim 4 (depends on 1)

The package structure of claim 1, wherein the distance between each array of bonding pads is about 50-90 μm.

### Claim 5

A package method for preventing gold bonding wires from collapsing, which is especially useful for those chips whose bonding pads are on the chip center to be packaged on a BGA substrate, wherein gold bonding wires bond two arrays of bonding pads on the chip center to the gold fingers before pouring liquid encapsulated epoxy into a mold, the package method comprising:
fixing the excessively long gold bonding wires to the chip with a epoxy strip outside the two arrays of bonding pads by a predetermined distance before packaging the gold bonding wire by pouring liquid encapsulated epoxy into a mold; or
adhering a dummy die to each outside of two arrays of bonding pads of the chip which has a plurality of redistribution layers respectively corresponding to the bonding pads, and
connecting one segment of the gold bonding wires to one end of redistribution layer through the bonding pad, and connecting another segment of the gold bonding wires to the gold finger of the BGA substrate through the other end of the redistribution layer.