# US 2008/0185711 A1 · Semiconductor package substrate > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2008/0185711 A1 - Document ID: US20080185711A1 - Status: Published application - Kind: A1 - Application number: 11/852,287 - Filed: 2007-09-08 - Published: 2008-08-07 - Earliest claimed: 2007-02-02 - Assignees: Phoenix Precision Technology Corporation - Inventors: Shih-Ping Hsu - Web page: https://patentgrep.com/patent/US20080185711A1 ## CPC - H05K 3/243: {characterised by selective plating, e.g. for finish plating of pads (selective plating for making the circuit pattern H05K3/108, H05K3/182)} - H05K 3/4007: {Surface contacts, e.g. bumps (H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3465)} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/652: Cross-sectional shapes - H10W 70/687: {characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H05K 3/108: {by semi-additive methods; masks therefor (characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241)} - H05K 3/28: Applying non-metallic protective coatings {(H05K3/0091 takes precedence; methods for intermediate insulating layers for build-up multilayer circuits H05K3/4673)} - H05K 2201/0367: Metallic bump or raised conductor not used as solder bump - H05K 2203/0574: Stacked resist layers used for different processes - H10W 72/07251: {characterised by changes in properties of the bump connectors during connecting} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/90: Bond pads, in general - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package substrate structure includes a circuit board with a plurality of first connection pads formed on at least a surface thereof; conductive posts formed on the surfaces of the first connection pads; and an insulative protection layer formed on the surface of the circuit board and having openings formed to completely expose the conductive posts, the conductive posts protruding above the surface of the substrate, thereby the electrical connection between the conductive posts and a semiconductor chip is facilitated, and the quality and the reliability of subsequent packaging process are ensured. ## Claims ### Claim 1 A semiconductor package substrate, comprising: a circuit board having a plurality of first connection pads formed on at least a surface thereof; a plurality of conductive posts formed on the surfaces of the corresponding first connection pads by electroplating; and an insulative protection layer formed on the surface of the circuit board and having openings formed to completely expose the conductive posts, the conductive posts protruding above surface of the insulative protection layer to allow mounting of a semiconductor chip. ### Claim 2 (depends on 1) The semiconductor package substrate as claimed in claim 1, wherein the circuit board further comprises a plurality of circuits formed on a surface thereof. ### Claim 3 (depends on 1) The semiconductor package substrate as claimed in claim 1, wherein the outer diameters of the conductive posts are equal to or smaller than those of the first connection pads. ### Claim 4 (depends on 1) The semiconductor package substrate as claimed in claim 1, wherein the first connection pads are solder pads. ### Claim 5 (depends on 1) The semiconductor package substrate as claimed in claim 1, wherein the insulative protection layer is made up of a photosensitive dielectric material. ### Claim 6 (depends on 5) The semiconductor package substrate as claimed in claim 5, wherein the photosensitive dielectric material is in the form of a dry film or liquid. ### Claim 7 (depends on 1) The semiconductor package substrate as claimed in claim 1, further comprising an adhesive layer formed on the surfaces of the conductive posts. ### Claim 8 (depends on 7) The semiconductor package substrate as claimed in claim 7, wherein the adhesive layer is made up of a material selected from the group consisting of chemically deposited Ni/Au, chemically deposited Sn, chemically deposited Ni/Pd/Au, electroplated Ni/Au, electroplated Sn, electroplated Sn/Pb, organic solder protection (OSP) layer and direct immerging gold. ### Claim 9 (depends on 1) The semiconductor package substrate as claimed in claim 1, further comprising a plurality of conductive elements formed on the surfaces of the conductive posts. ### Claim 10 (depends on 9) The semiconductor package substrate as claimed in claim 9, wherein the conductive elements are solder bumps. ### Claim 11 A semiconductor package substrate, comprising: a circuit board having a plurality of first connection pads and second connection pads formed on at least a surface thereof; a plurality of conductive posts formed on the surfaces of the first connection pads by electroplating; and an insulative protection layer formed on the surface of the circuit board, and having openings formed to completely expose the conductive posts, the conductive posts protruding above the surface of the insulative protection layer to allow mounting of a semiconductor chip, and the insulative protection layer further having openings formed for exposing the second connection pads. ### Claim 12 (depends on 11) The semiconductor package substrate as claimed in claim 11, wherein circuits are formed on the surface of the circuit board. ### Claim 13 (depends on 11) The semiconductor package substrate as claimed in claim 11, wherein the outer diameters of the conductive posts are equal to or smaller than those of the first connection pads. ### Claim 14 (depends on 11) The semiconductor package substrate as claimed in claim 11, wherein the first connection pads are solder pads. ### Claim 15 (depends on 11) The semiconductor package substrate as claimed in claim 11, wherein the second connection pads are wire bonding pads, which are lower than the surface of the insulative protection layer. ### Claim 16 (depends on 11) The semiconductor package substrate as claimed in claim 11, wherein the insulative protection layer is made up of a photosensitive dielectric material. ### Claim 17 (depends on 16) The semiconductor package substrate as claimed in claim 16, wherein the photosensitive dielectric material is in the form of a dry film or liquid. ### Claim 18 (depends on 11) The semiconductor package substrate as claimed in claim 11, further comprising an adhesive layer formed on the surfaces of the conductive posts and the second connection pads. ### Claim 19 (depends on 18) The semiconductor package substrate as claimed in claim 18, wherein the adhesive layer is made of a material selected from the group consisting of chemically deposited Ni/Au, chemically deposited Sn, chemically deposited Ni/Pd/Au, electroplated Ni/Au, electroplated Sn, electroplated Sn/Pb, organic solder protection (OSP) layer and direct immerging gold. ### Claim 20 (depends on 11) The semiconductor package substrate of claim 11, further comprising a plurality of conductive elements formed on the surfaces of the conductive posts. ### Claim 21 (depends on 20) The semiconductor package substrate of claim 20, wherein the conductive elements are solder bumps.