# US 2008/0185697 A1 · Chip package structure and method of fabricating the same

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- Number: US 2008/0185697 A1
- Document ID: US20080185697A1
- Status: Published application
- Kind: A1
- Application number: 11/734,250
- Filed: 2007-04-11
- Published: 2008-08-07
- Earliest claimed: 2007-02-06
- Assignees: ChipMOS Technologies (Bermuda) Ltd.
- Inventors: Jie-Hung Chiou; Yong-Chao Qiao; Yan-Yi Wu
- Web page: https://patentgrep.com/patent/US20080185697A1

## CPC

- H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)}
- H10W 70/042: {Etching}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 72/073: {of die-attach connectors}
- H10W 72/075: {of bond wires}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/10: characterised by their shape or disposition
- H10W 74/127: {characterised by arrangements for sealing or adhesion}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of fabricating a chip package structure includes the steps of providing a lead frame having a die pad, plural leads and at least one structure enhancement element. A chip is then disposed on the die pad and plural bonding wires are formed to electrically connect the chip to the leads. Then, an upper encapsulant and a first lower encapsulant are formed on an upper surface and a lower surface of the lead frame, respectively. The first lower encapsulant has plural concaves to expose the structure enhancement element. Finally, the structure enhancement element is etched with use of the first lower encapsulant as an etching mask until the die pad and one of the leads connected by the structure enhancement element, or two of the adjacent leads connected thereby are electrically insulated.

## Claims

### Claim 1

A chip package structure, comprising:
a chip having an active surface, a back surface, and a plurality of chip bonding pads disposed on the active surface;
a lead frame having an upper surface and a lower surface corresponding to the upper surface, the lead frame comprising:
a die pad to which the back surface of the chip is adhered; and
a plurality of leads surrounding the die pad;
a plurality of bonding wires electrically connected to the chip bonding pads and to the leads, respectively;
an upper encapsulant encapsulating the chip, the bonding wires, and the upper surface of the lead frame; and
a first lower encapsulant encapsulating the lower surface of the lead frame, wherein the first lower encapsulant comprises at least a concave to expose the upper encapsulant filled either between the die pad and one of the leads or between two of the adjacent leads.

### Claim 2 (depends on 1)

The chip package structure of claim 1, further comprising a second lower encapsulant filled in the concave of the first lower encapsulant

### Claim 3

A chip package structure, comprising:
a chip having an active surface, a back surface, and a plurality of chip bonding pads disposed on the active surface;
a lead frame having an upper surface and a lower surface corresponding to the upper surface, the lead frame comprising:
a die pad to which the back surface of the chip is adhered; and
a plurality of leads surrounding the die pad;
a plurality of bonding wires electrically connected to the chip bonding pads and to the leads, respectively;
an upper encapsulant encapsulating the chip, the bonding wires, and the upper surface of the lead frame; and
a lower encapsulant filled between the die pad and the leads.

### Claim 4 (depends on 3)

The chip package structure of claim 3, further comprising an etching mask disposed on the lower surface of the lead frame.

### Claim 5 (depends on 4)

The chip package structure of claim 4, further comprising a lower encapsulant filled between the die pad and the etching mask.

### Claim 6 (depends on 5)

The chip package structure of claim 5, wherein the lower encapsulant further encapsulates the etching mask.

### Claim 7 (depends on 3)

The chip package structure of claim 3, further comprising an etching mask disposed on the lower surface of the leads.

### Claim 8 (depends on 7)

The chip package structure of claim 7, further comprising a lower encapsulant filled between the die pad and the leads, so as to expose the lower surface of the die pad.

### Claim 9 (depends on 3)

The chip package structure of claim 3, further comprising an etching mask disposed on the lower surface of the die pad.

### Claim 10 (depends on 3)

The chip package structure of claim 3, further comprising a lower encapsulant filled between the die pad and the leads, so as to expose the lower surface of the leads.

### Claim 11 (depends on 3)

The chip package structure of claim 3, wherein one of the die pad and the leads has a down-set design.

### Claim 12

A chip package structure, comprising:
a chip having an active surface, a back surface, and a plurality of chip bonding pads disposed on the active surface;
a lead frame having an upper surface and a lower surface corresponding to the upper surface, the lead frame comprising:
a die pad to which the back surface of the chip is adhered; and
a plurality of leads surrounding the die pad;
a plurality of bonding wires electrically connected to the chip bonding pads and to the leads, respectively;
an upper encapsulant encapsulating the chip, the bonding wires, and the upper surface of the lead frame; and
a lower encapsulant filled between the die pad and the leads and encapsulating the lower surface of the lead frame.

### Claim at position 13

13-22. (canceled)