# US 2008/0185687 A1 · Memory device and method for fabricating the same

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- Number: US 2008/0185687 A1
- Document ID: US20080185687A1
- Status: Published application
- Kind: A1
- Application number: 12/026,322
- Filed: 2008-02-05
- Published: 2008-08-07
- Earliest claimed: 2007-02-07
- Assignees: Industry-University Cooperation Foundation Hanyang University
- Inventors: Jin-Pyo Hong; Young-Ho Do; June-Sik Kwak; Koo-Woong Jeong; Min-Su Park
- Web page: https://patentgrep.com/patent/US20080185687A1

## CPC

- H10N 70/883: {Oxides or nitrides}
- H10N 70/026: {by physical vapor deposition, e.g. sputtering}
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A memory device includes a lower electrode layer formed over a substrate, a resistance layer including a metal nitride layer formed over the lower electrode layer, and an upper electrode layer formed over the resistance layer.

## Claims

### Claim 1

A memory device, comprising:
a lower electrode layer formed over a substrate;
a resistance layer including a metal nitride layer formed over the lower electrode layer; and
an upper electrode layer formed over the resistance layer.

### Claim 2 (depends on 1)

The device of claim 1, wherein the resistance layer has a high resistance state (HRS) or a low resistance state (LRS) corresponding to bit data ‘0’ or ‘1’ according to a bias applied to the lower and upper electrode layers.

### Claim 3 (depends on 1)

The device of claim 1, wherein the metal nitride layer includes an MN-based compound, M and N being metal and nitrogen, respectively.

### Claim 4 (depends on 3)

The device of claim 3, wherein the M includes one selected from a group consisting of aluminum (Al), iron (Fe), cobalt (Co), chromium (Cr) and a combination thereof.

### Claim 5 (depends on 1)

The device of claim 1, wherein the metal nitride layer is made of aluminum nitride (AlN).

### Claim 6 (depends on 2)

The device of claim 2, wherein the HRS has resistivity approximately 100 to approximately 8,000 times greater than the LRS.

### Claim 7 (depends on 2)

The device of claim 2, wherein the HRS has resistivity approximately 250 to approximately 5,000 times greater than the LRS.

### Claim 8 (depends on 5)

The device of claim 5, wherein the HRS has resistivity approximately 300 times greater than the LRS.

### Claim 9 (depends on 1)

The device of claim 1, wherein the metal nitride layer has a thickness of approximately 10 nm to approximately 500 nm.

### Claim 10 (depends on 1)

The device of claim 1, wherein the metal nitride layer has a thickness of approximately 50 nm to approximately 200 nm.

### Claim 11 (depends on 1)

The device of claim 1, wherein the substrate is one of a silicon (Si) substrate, a silicon oxide (SiO2) substrate, a multi-layered substrate of Si and SiO2, and a polysilicon substrate.

### Claim 12 (depends on 1)

The device of claim 1, wherein each of the lower and the upper electrode layers includes one selected from a group consisting of platinum (Pt), gold (Au), aluminum (Al), copper (Cu), titanium (Ti), and a combination thereof, the lower and the upper electrode layer being made of the same or different materials.

### Claim 13

A non-volatile resistive random access memory (ReRAM) device, comprising:
a lower electrode layer formed over a substrate;
a resistance layer including a metal nitride layer formed over the lower electrode layer; and
an upper electrode layer formed over the resistance layer.

### Claim 14 (depends on 13)

The device of claim 13, wherein the resistance layer has in a HRS or a LRS corresponding to bit data ‘0’ or ‘1’ according to a bias applied to the lower and the upper electrode layers.

### Claim 15 (depends on 13)

The device of claim 13, wherein the metal nitride layer includes an MN-based compound, M and N being metal and nitrogen, respectively.

### Claim 16 (depends on 15)

The device of claim 15, wherein the M includes one selected from a group consisting of Al, Fe, Co, Cr, and a combination thereof.

### Claim 17 (depends on 13)

The device of claim 13, wherein the metal nitride layer is made of AlN.

### Claim 18 (depends on 14)

The device of claim 14, wherein the HRS has resistivity approximately 100 to approximately 8,000 times greater than the LRS.

### Claim 19 (depends on 14)

The device of claim 14, wherein the HRS has resistivity approximately 250 to approximately 5,000 times greater than the LRS.

### Claim 20 (depends on 17)

The device of claim 17, wherein the HRS has resistivity approximately 300 times greater than the LRS.

### Claim 21 (depends on 13)

The device of claim 13, wherein the metal nitride layer has a thickness of approximately 10 nm to approximately 500 nm.

### Claim 22 (depends on 13)

The device of claim 13, wherein the metal nitride layer has a thickness of approximately 50 nm to approximately 200 nm.

### Claim 23 (depends on 13)

The device of claim 13, wherein the substrate is one of a Si substrate, a SiO2 substrate, a multi-layered substrate of Si and SiO2, and a polysilicon substrate.

### Claim 24 (depends on 13)

The device of claim 13, wherein each of the lower and the upper electrode layers includes one selected from a group consisting of Pt, Au, Al, Cu, Ti, and a combination thereof, the lower and the upper electrode layer being made of the same or different materials.

### Claim 25

A method for fabricating a memory device, the method comprising:
providing a substrate;
forming a lower electrode layer over the substrate;
forming a resistance layer including a metal nitride layer over the lower electrode layer; and
forming an upper electrode layer over the resistance layer.

### Claim 26 (depends on 25)

The method of claim 25, after forming the resistance layer, further comprising performing a thermal treatment on the substrate where the lower electrode layer and the resistance layer are formed.

### Claim 27 (depends on 25)

The method of claim 25, wherein the metal nitride layer includes an MN-based compound, M and N being metal and nitrogen, respectively.

### Claim 28 (depends on 27)

The method of claim 27, wherein the M includes one selected from a group consisting of Al, Fe, Co, Cr and a combination thereof.

### Claim 29 (depends on 25)

The method of claim 25, wherein the metal nitride layer is made of AlN.

### Claim 30 (depends on 25)

The method of claim 25, wherein each of the lower electrode layer, the metal nitride layer, and the upper electrode layer is formed by performing one of physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering, pulsed laser deposition (PLD), thermal evaporation, electron beam evaporation, atomic layer deposition (ALD), and molecular beam epitaxy (MBE) processes.

### Claim 31 (depends on 25)

The method of claim 25, wherein the metal nitride layer is formed by performing a sputtering process.

### Claim 32 (depends on 31)

The method of claim 31, wherein the metal nitride layer is formed using a gas mixture of argon (Ar) and nitrogen (N2) at a pressure in the range of approximately 3 mTorr to approximately 10 mTorr, the nitrogen gas occupying approximately 10% to approximately 50% of the gas mixture.

### Claim 33 (depends on 26)

The method of claim 26, wherein the thermal treatment is performed at a temperature in the range of approximately 600° C. to approximately 900° C.

### Claim 34 (depends on 26)

The method of claim 26, wherein the thermal treatment is performed at a temperature in the range of approximately 100° C. to approximately 1,000° C.

### Claim 35 (depends on 26)

The method of claim 26, wherein the thermal treatment is performed under a N2 atmosphere where a N2 gas is applied at a partial pressure of approximately 100 Torr to approximately 500 Torr, or a vacuum condition.

### Claim 36

A method for fabricating a non-volatile ReRAM device, the method comprising:
providing a substrate;
forming a lower electrode layer over the substrate;
forming a resistance layer including a metal nitride layer over the lower electrode layer; and
forming an upper electrode layer over the resistance layer.

### Claim 37 (depends on 36)

The method of claim 36, after forming the resistance layer, further comprising performing a thermal treatment on the substrate where the lower electrode layer and the resistance layer are formed.

### Claim 38 (depends on 36)

The method of claim 36, wherein the metal nitride layer includes an MN-based compound, M and N being metal and nitrogen, respectively.

### Claim 39 (depends on 38)

The method of claim 38, wherein the M includes one selected from a group consisting of Al, Fe, Co, Cr and a combination thereof.

### Claim 40 (depends on 36)

The method of claim 36, wherein the metal nitride layer is made of AlN.

### Claim 41 (depends on 36)

The method of claim 36, wherein each of the lower electrode layer, the metal nitride layer, and the upper electrode layer is formed by performing one of PVD, CVD, PLD, thermal evaporation, electron beam evaporation, ALD, and MBE processes.

### Claim 42 (depends on 36)

The method of claim 36, wherein the metal nitride layer is formed by performing a sputtering process.

### Claim 43 (depends on 36)

The method of claim 36, wherein the metal nitride layer is formed using a gas mixture of argon (Ar) and nitrogen (N2) at a pressure in the range of approximately 3 mTorr to approximately 10 mTorr, the nitrogen gas occupying approximately 10% to approximately 50% of the gas mixture.

### Claim 44 (depends on 37)

The method of claim 37, wherein the thermal treatment is performed at a temperature in the range of approximately 600° C. to approximately 900° C.

### Claim 45 (depends on 37)

The method of claim 37, wherein the thermal treatment is performed at a temperature in the range of approximately 100° C. to approximately 1,000° C.

### Claim 46 (depends on 37)

The method of claim 37, wherein the thermal treatment is performed under a N2 atmosphere where a N2 gas is applied at a partial pressure of approximately 100 Torr to approximately 500 Torr, or a vacuum condition.